Lines Matching refs:in

19 	in guest RAM. This memory is expected to hold a copy of the following
28 	whose data will be filled in by the hypervisor. The hypervisor is only
35 		An odd version indicates an in-progress update.
47 	Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
52 	data: 4-byte aligned physical address of a memory area which must be in
53 	guest RAM, plus an enable bit in bit 0. This memory is expected to hold
67 	whose data will be filled in by the hypervisor periodically. Only one
77 		An odd version indicates an in-progress update.
109 		flags: bits in this field indicate extended capabilities
111 		of specific flags has to be checked in 0x40000001 cpuid leaf.
122 			    |		   | See 4.70 in api.txt
125 	Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
133 	This MSR falls outside the reserved KVM range and may be removed in the
136 	Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
143 	This MSR falls outside the reserved KVM range and may be removed in the
146 	Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
168 	64 byte memory area which must be in guest RAM and must be
172 	when vcpu is in cpl == 0.
204 	in guest RAM, plus an enable bit in bit 0. This memory is expected to
214 	whose data will be filled in by the hypervisor periodically. Only one
226 		in-progress update.
229 		changes in this structure in the future.
231 		steal: the amount of time in which this vCPU did not run, in
239 	physical address of a 4 byte memory area which must be in guest RAM and
246 	EOI by clearing the bit in guest memory - this location will
254 	significant bit while in the current VCPU context, this means that
260 	guest and clear the least significant bit in the memory area
261 	in the window between guest testing it to detect
264 	guest must both read the least significant bit in the memory area and