Lines Matching refs:we

11                on an emulated mmu except for timing (we attempt to comply
62 - when guest paging is disabled, we translate guest physical addresses to
64 - when guest paging is enabled, we translate guest virtual addresses, to
66 - when the guest launches a guest of its own, we translate nested guest
254 A tlb flush means that we need to synchronize all sptes reachable from the
255 guest's cr3.  This is expensive, so we keep all guest page tables write
263 the amount of emulation we have to do when the guest modifies multiple gptes,
267 As a side effect we have to resynchronize all reachable unsynchronized shadow
310    - if successful, we can let the guest continue and modify the gpte
344 we cannot map the permissions for gpte.u=1, gpte.w=0 to any spte (the
358 - if CR4.SMEP is enabled: since we've turned the page into a kernel page,
360   If we get a user fetch or read fault, we'll change spte.u=1 and
366   here we do not care the case that CR4.SMAP is enabled since KVM will
370 from being written by the kernel after cr0.wp has changed to 1, we make
453 want to use an MMIO sptes created with an odd generation number, and we can do