Lines Matching refs:spte

42 spte  shadow pte (referring to pfns)
109 A nonleaf spte allows the hardware mmu to reach the leaf pages and
112 A leaf spte corresponds to either one or two translations encoded into
206     parent_ptes bit 0 is zero, only one spte points at this pages and
207     parent_ptes points at this single spte, otherwise, there exists multiple
228     Only present on 32-bit hosts, where a 64-bit spte cannot be written
292    - check for valid generation number in the spte (see "Fast invalidation of
305  - walk the shadow page table to find the spte for the translation,
307    - If this is an mmio request, cache the mmio info to the spte and set some
308      reserved bit on the spte (see callers of kvm_mmu_set_mmio_spte_mask)
344 we cannot map the permissions for gpte.u=1, gpte.w=0 to any spte (the
350 - kernel write fault: spte.u=0, spte.w=1 (allows full kernel access,
352 - read fault: spte.u=1, spte.w=0 (allows full read access, disallows kernel
359   the kernel may now execute it.  We handle this by also setting spte.nx.
360   If we get a user fetch or read fault, we'll change spte.u=1 and
361   spte.nx=gpte.nx back.  For this to work, KVM forces EFER.NX to 1 when
369 To prevent an spte that was converted into a kernel page with cr0.wp=0
371 the value of cr0.wp part of the page role.  This means that an spte created
374 exists when an spte created with cr0.wp=0 and cr4.smep=0 is used after
386 To instantiate a large spte, four constraints must be satisfied:
388 - the spte must point to a large host page
391 - if the spte will be writeable, the large page frame may not overlap any
398 a large spte.  The frames at the end of an unaligned memory slot have
437 When KVM finds an MMIO spte, it checks the generation number of the spte.
438 If the generation number of the spte does not equal the global generation
442 Since only 19 bits are used to store generation-number on mmio spte, all
447 stored into the MMIO spte.  Thus, the MMIO spte might be created based on
454 this without losing a bit in the MMIO spte.  The low bit of the generation
455 is not stored in MMIO spte, and presumed zero when it is extracted out of the
456 spte.  If KVM is unlucky and creates an MMIO spte while the low bit is 1,
457 the next access to the spte will always be a cache miss.