Lines Matching refs:or

8 Only one VGIC instance may be instantiated through either this API or the
52     GICv2 specs.  Getting or setting such a register has the same effect as
53     reading or writing the register on the actual hardware from the cpu whose
61     -ENXIO: Getting or setting this register is not yet supported
62     -EBUSY: One or more VCPUs are running
74     defined in the GICv2 specs.  Getting or setting such a register has the
75     same effect as reading or writing the register on the actual hardware.
85     Thus, preemption level X has one or more active interrupts if and only if:
95     -ENXIO: Getting or setting this register is not yet supported
96     -EBUSY: One or more VCPUs are running
106     -EBUSY: Value has already be set, or GIC has already been initialized