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1 This page describes the structures and procedures used by the cx2341x DMA
8 engine to efficiently transfer large volumes of data between the card and main
15 contiguous buffer, the driver can allocate several smaller buffers.
17 In practice, I've seen the average transfer to be roughly 80K, but transfers
19 important, because that is the largest block that the kernel can normally
20 allocate. Even still, 128K blocks are hard to come by, so the driver writer is
21 urged to choose a smaller block size and learn the scatter-gather technique.
25 Note: the hardware expects little-endian data ('intel format').
30 This section describes, in general, the order of events when handling DMA
33 - The card raises the Encoder interrupt.
34 - The driver reads the transfer type, offset and size from Mailbox #10.
35 - The driver constructs the scatter-gather array from enough free dma buffers
36   to cover the size.
37 - The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
38 - The card raises the DMA Complete interrupt.
39 - The driver checks the DMA status register for any errors.
40 - The driver post-processes the newly transferred buffers.
42 NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
43 simultaneously. (End of the last, start of the next, etc.)
52 Results[1]: Offset: The position relative to the card's memory space.
55 My speculation is that since the StartCapture API has a capture type of "RAW"
56 available, that the type field will have other values that correspond to YUV
63 tells the card the source and destination of each data-block to transfer.
64 Card "addresses" are derived from the offset supplied by Mailbox #10. Host
65 addresses are the physical memory location of the target DMA buffer.
68 the source address, the second is the destination address. Both take up the
69 entire 32 bits. The lowest 18 bits of the third word is the transfer byte
70 count. The high-bit of the third word is the "last" flag. The last-flag tells
71 the card to raise the DMA_DONE interrupt. From hard personal experience, if
72 you forget to set this bit, the card will still "work" but the stream will
75 The transfer count must be a multiple of 256. Therefore, the driver will need
76 to track how much data in the target buffer is valid and deal with it
83 - 14-bit reserved (high bit is the last flag)
89 Register 0x0004 holds the DMA Transfer Status: