Lines Matching refs:the

2 Below is what the bt878 data book says about the PCI bug compatibility
3 modes of the bt878 chip.
5 The triton1 insmod option sets the EN_TBFX bit in the control register.
6 The vsfx insmod option does the same for EN_VSFX bit.  If you have
11 enabled automagically for known-buggy chipsets (look at the kernel
23 The PCI REQ signal is the logical-or of the incoming function requests.
25 demultiplexed by the audio request signal. Thus the arbiter defaults to
26 the video function at power-up and parks there during no requests for
27 bus access. This is desirable since the video will request the bus more
28 often. However, the audio will have highest bus access priority. Thus
29 the audio will have first access to the bus even when issuing a request
30 after the video request but before the PCI external arbiter has granted
31 access to the Bt879. Neither function can preempt the other once on the
32 bus. The duration to empty the entire video PCI FIFO onto the PCI bus is
33 very short compared to the bus access latency the audio PCI FIFO can
40 When using the 430FX PCI, the following rules will ensure
43  (1) Deassert REQ at the same time as asserting FRAME.
45      finish-ing the previous transaction.
47 Since the individual bus masters do not have direct control of REQ, a
48 simple logical-or of video and audio requests would violate the rules.
49 Thus, both the arbiter and the initiator contain 430FX compatibility
50 mode logic. To enable 430FX mode, set the EN_TBFX bit as indicated in
53 When EN_TBFX is enabled, the arbiter ensures that the two compatibility
54 rules are satisfied. Before GNT is asserted by the PCI arbiter, this
55 internal arbiter may still logical-or the two requests. However, once
56 the GNT is issued, this arbiter must lock in its decision and now route
57 only the granted request to the REQ pin. The arbiter decision lock
58 happens regardless of the state of FRAME because it does not know when
60 the cycle following GNT). When FRAME is asserted, it is the initiator s
61 responsibility to remove its request at the same time. It is the
63 not allow the other request to hold REQ asserted. The decision lock may
64 be removed at the end of the transaction: for example, when the bus is
73 during the same cycle that GNT is de-asserted. This is non PCI 2.1
75 controllers, the EN_VSFX bit must be enabled (refer to Device Control
76 Register on page 104). When in this mode, the arbiter does not pass GNT
77 to the internal functions unless REQ is asserted. This prevents a bus
78 transaction from starting the same cycle as GNT is de-asserted. This
79 also has the side effect of not being able to take advantage of bus
81 query for these non-compliant devices, and set the EN_VSFX bit only if