Lines Matching refs:PCI

26 and requires root privileges to access things like PCI configuration
30 KVM PCI specific device assignment code as well as provide a more
57 could be anything from a multi-function PCI device with backdoors
58 between functions to a non-PCI-ACS (Access Control Services) capable
60 can also play a factor in terms of hiding devices.  A PCIe-to-PCI
119 Assume user wants to access PCI device 0000:06:0d.0
150 This device is behind a PCIe-to-PCI bridge[4], therefore we also
155 support PCI bridges).
224 		 * For PCI devices, config space is a region */
295 (PE is often a PCI domain but not always).
299 2) The hardware supports so called DMA windows - the PCI address range
314 and bridge structures above the multiple IOAs). PPC64 guests detect PCI errors
321 		of the DMA window on the PCI bus.
402 	/* When 0xFF's returned from reading PCI config space or IO BARs
403 	 * of the PCI device. Check the PE's state to see if that has been
408 	/* Waiting for pending PCI transactions to be completed and don't
409 	 * produce any more PCI traffic from/to the affected PE until
414 	 * standard part of PCI config space, AER registers are dumped
422 	 * is enough. However, the firmware of some PCI adapters would
430 	/* Configure the PCI bridges for the affected PE */
439 	 * start PCI traffic to/from the affected PE.
468 a PCI bus with a variable page size. Two ioctls have been added to support
495 access to things like PCI config space through MMIO registers.  To
497 IOMMU driver to group multi-function PCI devices together
499 still provide isolation.  For PCI, SR-IOV Virtual Functions are the
508 [4] In this case the device is below a PCI bridge, so transactions
514 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)