Lines Matching refs:the
5 its use by user programs. It is not currently used by the kernel itself.
40 /* Retry the transaction if it failed because it conflicted with
45 The 'tbegin' instruction denotes the start point, and 'tend' the end point.
46 Between these points the processor is in 'Transactional' state; any memory
48 transactional or non-transactional accesses within the system. In this
49 example, the transaction completes as though it were normal straight-line code
51 atomic move of money from the current account to the savings account has been
52 performed. Even though the normal ld/std instructions are used (note no
56 If, in the meantime, there is a conflict with the locations accessed by the
57 transaction, the transaction will be aborted by the CPU. Register and memory
58 state will roll back to that at the 'tbegin', and control will continue from
59 'tbegin+4'. The branch to abort_handler will be taken this second time; the
60 abort handler can check the cause of the failure, and retry.
63 and a few other status/flag regs; see the ISA for details.
71 - See the ISA for full documentation of everything that will abort transactions.
77 Syscalls made from within an active transaction will not be performed and the
78 transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL
82 the transaction is not explicitly doomed by the kernel. However, what the
83 kernel does to perform the syscall may result in the transaction being doomed
84 by the hardware. The syscall is performed in suspended mode so any side
86 guarantees are provided by the kernel about which syscalls will affect
90 if the calls are made via a library. Libraries may cache values (which may
91 give the appearance of success) or perform operations that cause transaction
92 failure before entering the kernel (which may produce different failure codes).
100 thread state (ucontext/mcontext) to represent the second transactional register
102 abort transactions. The usual ucontext_t passed to the signal handler
103 represents the checkpointed/original register state; the signal appears to have
106 If the sighandler ucontext has uc_link set, a second ucontext has been
107 delivered. For future compatibility the MSR.TS field should be checked to
108 determine the transactional state -- if so, the second ucontext in uc->uc_link
109 represents the active transactional registers at the point of the signal.
112 field shows the transactional mode.
114 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
115 bits are stored in the MSR of the second ucontext, i.e. in
116 uc->uc_link->uc_mcontext.regs->msr. The top word contains the transactional
120 and simply returning from the handler will deal with things correctly:
122 Transaction-aware signal handlers can read the transactional register state
123 from the second ucontext. This will be necessary for crash handlers to
124 determine, for example, the address of the instruction causing the SIGSEGV.
152 the stack. It's possible that the stack has moved back up after the tbegin.
153 The obvious case here is when the tbegin is called inside a function that
154 returns before a tend. In this case, the stack is part of the checkpointed
156 suspend, we are in trouble because if we get a tm abort, the program counter and
157 stack pointer will be back at the tbegin but our in memory stack won't be valid
161 the stack pointer from the checkpointed state, rather than the speculated
162 state. This ensures that the signal context (written tm suspended) will be
163 written below the stack required for the rollback. The transaction is aborted
164 because of the treclaim, so any memory written between the tbegin and the
167 For signals taken in non-TM or suspended mode, we use the
174 These are defined in <asm/reg.h>, and distinguish different reasons why the
186 These can be checked by the user program's abort handler as TEXASR[0:7]. If
187 bit 7 is set, it indicates that the error is consider persistent. For example
194 it looks like the transaction has just started (the checkpointed state is
195 presented). The transaction cannot then be continued and will take the failure
196 handler route. Furthermore, the transactional 2nd register state will be