Lines Matching refs:We

46     We call this the RTT.
78 	32-bit PCIe accesses.  We configure that window at boot from FW and
92     SR-IOV).  We basically use the trick of forcing the bridge MMIO windows
117     We have code (fairly new compared to the M32 stuff) that exploits that
120     We configure an M64 window to cover the entire region of address space
122     for the M32, it comes out of a different "reserve").  We configure it
130     - We do the PE# allocation *after* the 64-bit space has been assigned
131       because the addresses we use directly determine the PE#.  We then
135     - We cannot "group" segments in HW, so if a device ends up using more
140       SW.  We lose a bit of effectiveness of EEH in that case, but that's
142       other ones for that "domain".  We thus introduce the concept of
146     We would like to investigate using additional M64 windows in "single
216   We decide to leverage this M64 window to map VFs to individual PEs, since