Lines Matching refs:D3
81 The PCI PM Spec defines 4 operating states for devices (D0-D3) and for buses
86 There are two variants of the D3 state defined by the specification. The first
87 one is D3hot, referred to as the software accessible D3, because devices can be
114 | D0 | D1, D2, D3 |
116 | D1 | D2, D3 |
118 | D2 | D3 |
120 | D1, D2, D3 | D0 |
129 while in a low-power state (D1-D3), but they are not required to be capable
161 labeled as D0, D1, D2, and D3 that roughly correspond to the native PCI PM
162 D0-D3 states (although the difference between D3hot and D3cold is not taken
173 is going to be put into a low-power state (D1-D3) and is supposed to generate
178 _OFF control methods). If the current power state of the device is D3, it can
316 unsigned int d3_delay; /* D3->D0 transition time in ms */