Lines Matching refs:the
6 This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
16 This driver supports both the platform bus and PCI.
25 CONFIG_STMMAC_PLATFORM: is to enable the platform driver.
26 CONFIG_STMMAC_PCI: is to enable the pci driver.
30 phyaddr: to manually provide the physical address to the PHY device;
34 tc: control the HW FIFO threshold;
48 The xmit method is invoked when the kernel needs to transmit a packet; it sets
49 the descriptors in the ring and informs the DMA engine that there is a packet
51 By default, the driver sets the NETIF_F_SG bit in the features field of the
52 net_device structure enabling the scatter-gather feature. This is true on
53 chips and configurations where the checksum can be done in hardware.
54 Once the controller has finished transmitting the packet, napi will be
55 scheduled to release the transmit resources.
59 are not queued so the driver has to scan all the descriptors in the ring during
60 the receive process.
61 This is based on NAPI so the interrupt handler signals only if there is work
63 Then the poll method will be scheduled at some future point.
64 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
65 buffers in order to avoid the memcpy (zero-copy).
68 The driver is able to mitigate the number of its DMA interrupts
69 using NAPI for the reception on chips older than the 3.50.
74 Wake up on Lan feature through Magic and Unicast frames are supported for the
84 buffer pointer. RING mode is the default.
87 the list, hence creating the explicit chaining in the descriptor itself,
91 The extended descriptors give us information about the Ethernet payload
93 These are not available on GMAC Synopsys chips older than the 3.50.
94 At probe time the driver will decide if these can be actually used.
95 This support also is mandatory for PTPv2 because the extra descriptors
96 are used for saving the hardware timestamps and Extended Status.
106 Jumbo frames are supported and tested for the GMAC.
115 Several information can be passed through the platform and device-tree.
144 o phy_bus_name: phy bus name to attach to the stmmac.
146 o phy_addr: the physical address can be passed from the platform.
147 If it is set to -1 the driver will automatically
148 detect it at run-time by probing all the 32 addresses.
150 o mdio_bus_data: specific platform fields for the MDIO bus.
152 o pbl: the Programmable Burst Length is maximum number of beats to
154 GMAC also enables the 4xPBL by default.
157 o has_gmac: uses the GMAC core.
158 o enh_desc: if sets the MAC will use the enhanced descriptor structure.
159 o tx_coe: core is able to perform the tx csum in HW.
160 o rx_coe: the supports three check sum offloading engine types:
162 o bugged_jumbo: some HWs are not able to perform the csum in HW for
164 Setting this flag the csum will be done in SW on
166 o pmt: core has the embedded power module (optional).
167 o force_sf_dma_mode: force DMA to use the Store and Forward mode
168 instead of the Threshold.
169 o force_thresh_dma_mode: force DMA to use the Threshold mode other than
170 the Store and Forward mode.
171 o riwt_off: force to disable the RX watchdog feature and switch to NAPI mode.
173 (on ST SoCs) according to the link speed negotiated by the
175 o bus_setup: perform HW setup of the bus. For example, on some ST platforms
176 this field is used to configure the AMBA bridge to generate more
180 where the HW needs to have set some PIO lines or system cfg
195 o phy_reset: hook to reset the phy device attached to the bus.
196 o phy_mask: phy mask passed when register the MDIO bus within the driver.
200 For DMA engine we have the following internal fields that should be
201 tuned according to the HW capabilities.
211 o fixed_burst: program the DMA to use the fixed burst mode
212 o burst_len: this is the value we put in the register
218 Below an example how the structures above are using on ST platforms.
226 | on this platform when the
233 | all the resources necessary
238 Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact,
245 |-> function to provide the phy_reset on this board
255 During the board's device_init we can configure the first
258 and the second one, with a real PHY device attached to the bus,
259 by using the stmmac_mdio_bus_data structure (to provide the id, the
262 Note that, starting from new chips, where it is available the HW capability
265 available. As strategy adopted in this driver, the information from the HW
266 capability register can replace what has been passed from the platform.
270 Please see the following document:
273 4.11) This is a summary of the content of some relevant files:
274 o stmmac_main.c: to implement the main network device driver;
276 o stmmac_pci: this the PCI driver;
277 o stmmac_platform.c: this the platform driver (OF supported)
278 o stmmac_ethtool.c: to implement the ethtool support;
283 o dwmac1000_dma.c: dma functions for the GMAC chip;
284 o dwmac1000.h: specific header file for the dwmac GiGa;
286 o dwmac100_dma.c: dma functions for the dwmac 100 chip;
287 o dwmac1000.h: specific header file for the MAC;
295 o dwmac-<XXX>.c: these are for the platform glue-logic file; e.g. dwmac-sti.c
303 These can be read in several ways depending on the
304 type of the information actually needed.
306 For example a user can be use the ethtool support
308 (that shows the Management counters (MMC) if supported)
309 or sees the MAC/DMA registers: e.g. using: ethtool -d ethX
311 Compiling the Kernel with CONFIG_DEBUG_FS the driver will export the following
315 To show the DMA TX/RX descriptor rings
317 Developer can also use the "debug" module parameter to get further debug
323 with a family of Physical layer to operate in the Low power Idle(LPI)
324 mode. The EEE mode supports the IEEE 802.3 MAC operation at 100Mbps,
327 The LPI mode allows power saving by switching off parts of the
329 transmitted & received. The system on both the side of the link can
330 disable some functionalities & save power during the period of low-link
331 utilization. The MAC controls whether the system should enter or exit
332 the LPI mode & communicate this to PHY.
334 As soon as the interface is opened, the driver verifies if the EEE can
335 be supported. This is done by looking at both the DMA HW capability
336 register and the PHY devices MCD registers.
337 To enter in Tx LPI mode the driver needs to have a software timer
338 that enable and disable the LPI mode when there is nothing to be
342 The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP),
347 In addition to the basic timestamp features mentioned in IEEE 1588-2002
348 Timestamps, new GMAC cores support the advanced timestamp features.
349 IEEE 1588-2008 that can be enabled when configure the Kernel.
353 This information is available at run-time by looking at the
354 HW capability register. This means that the stmmac can manage
355 auto-negotiation and link status w/o using the PHYLIB stuff
356 In fact, the HW provides a subset of extended registers to
357 restart the ANE, verify Full/Half duplex mode and Speed.
358 Also thanks to these registers it is possible to look at the