Lines Matching refs:the

4 How significant is the cache maintenance overhead?
6 pre-fetch makes the cache overhead relatively significant. If the DMA
7 preparations for the next request are done in parallel with the current
8 transfer, the DMA preparation overhead would not affect the MMC performance.
9 The intention of non-blocking (asynchronous) MMC requests is to minimize the
11 Using mmc_wait_for_req(), the MMC controller is idle while dma_map_sg and
13 possible to prepare the caches for next job in parallel with an active
19 The mmc_blk_issue_rw_rq() in the MMC block driver is made non-blocking.
20 The increase in throughput is proportional to the time it takes to
22 a request and how fast the memory is. The faster the MMC/SD is the
23 more significant the prepare request time becomes. Roughly the expected
25 platform. In power save mode, when clocks run on a lower frequency, the DMA
27 in parallel with the transfer performance won't be affected.
40 for completion of that request and starts the new one and returns. It
41 doesn't wait for the new request to complete. If there is no ongoing
42 request it starts the new request and returns immediately.
47 There are two optional members in the mmc_host_ops -- pre_req() and
48 post_req() -- that the host driver may implement in order to move work
49 to before and after the actual mmc_host_ops.request() function is called.
50 In the DMA case pre_req() may do dma_map_sg() and prepare the DMA
51 descriptor, and post_req() runs the dma_unmap_sg().
53 Optimize for the first request
57 with the previous transfer, since there is no previous request.
60 the performance loss. A way to optimize for this is to split the current
61 request in two chunks, prepare the first chunk and start the request,
62 and finally prepare the second chunk and start the transfer.
67    /* start MMC transfer for the complete transfer size */
72     * The first chunk of the request should take the same time
73     * to prepare as the "MMC process command time".
75     * the transfer is delayed, guesstimate max 4k as first chunk size.
78     /* flush pending desc to the DMAC (dmaengine.h) */
84      * of the first chunk. If the MMC runs out of the first data chunk
85      * before this call, the transfer is delayed.