Lines Matching refs:the
55 (*) The effects of the cpu cache.
63 - And then there's the Alpha.
76 Consider the following abstract model of the system:
101 Each CPU executes a program that generates memory access operations. In the
103 perform the memory operations in any order it likes, provided program causality
104 appears to be maintained. Similarly, the compiler may also arrange the
105 instructions it emits in any order it likes, provided it doesn't affect the
106 apparent operation of the program.
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
113 For example, consider the following sequence of events:
121 The set of accesses as seen by the memory system in the middle can be arranged
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
155 There is an obvious data dependency here, as the value loaded into D depends on
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
163 Note that CPU 2 will never try and load C into D because the CPU will load P
164 into Q before issuing the load of *Q.
171 locations, but the order in which the control registers are accessed is very
174 port register (D). To read internal register 5, the following code might then
180 but this might show up as either of the following two sequences:
185 the second of which will almost certainly result in a malfunction, since it set
186 the address _after_ attempting to read the register.
199 the CPU will issue the following memory operations:
214 the CPU will only issue the following sequence of memory operations:
222 the CPU will only issue:
231 (*) It _must_not_ be assumed that the compiler will do what you want
233 WRITE_ONCE(). Without them, the compiler is within its rights to
235 the Compiler Barrier section.
238 in the order given. This means that for:
242 we may get any of the following sequences:
256 we may get any one of the following sequences:
281 in a given bitfield are protected by different locks, the compiler's
283 field to corrupt the value of an adjacent field.
287 the same size as "char", "short", "int" and "long". "Properly
288 aligned" means the natural alignment, thus no constraints for
292 guarantees were introduced into the C11 standard, so beware when
294 of the standard containing this guarantee is Section 3.14, which
308 structure declaration and the other is not, or if the two
312 bit-fields in the same structure if all members declared
313 between them are also bit-fields, no matter what the
323 What is required is some way of intervening to instruct the compiler and the
324 CPU to restrict the order.
327 ordering over the memory operations on either side of the barrier.
329 Such enforcement is important because the CPUs and other devices in a system
333 override or suppress these tricks, allowing the code to sanely control the
344 A write memory barrier gives a guarantee that all the STORE operations
345 specified before the barrier will appear to happen before all the STORE
346 operations specified after the barrier with respect to the other
347 components of the system.
352 A CPU can be viewed as committing a sequence of store operations to the
354 occur in the sequence _before_ all the stores after the write barrier.
357 dependency barriers; see the "SMP barrier pairing" subsection.
362 A data dependency barrier is a weaker form of read barrier. In the case
363 where two loads are performed such that the second depends on the result
364 of the first (eg: the first load retrieves the address to which the second
366 make sure that the target of the second load is updated before the address
367 obtained by the first load is accessed.
373 As mentioned in (1), the other CPUs in the system can be viewed as
374 committing sequences of stores to the memory system that the CPU being
375 considered can then perceive. A data dependency barrier issued by the CPU
377 load touches one of a sequence of stores from another CPU, then by the
378 time the barrier completes, the effects of all the stores prior to that
379 touched by the load will be perceptible to any loads issued after the data
382 See the "Examples of memory barrier sequences" subsection for diagrams
383 showing the ordering constraints.
385 [!] Note that the first load really has to have a _data_ dependency and
386 not a control dependency. If the address for the second load is dependent
387 on the first load, but the dependency is through a conditional rather than
388 actually loading the address itself, then it's a _control_ dependency and
389 a full read barrier or better is required. See the "Control dependencies"
393 write barriers; see the "SMP barrier pairing" subsection.
398 A read barrier is a data dependency barrier plus a guarantee that all the
399 LOAD operations specified before the barrier will appear to happen before
400 all the LOAD operations specified after the barrier with respect to the
401 other components of the system.
410 see the "SMP barrier pairing" subsection.
415 A general memory barrier gives a guarantee that all the LOAD and STORE
416 operations specified before the barrier will appear to happen before all
417 the LOAD and STORE operations specified after the barrier with respect to
418 the other components of the system.
431 operations after the ACQUIRE operation will appear to happen after the
432 ACQUIRE operation with respect to the other components of the system.
446 memory operations before the RELEASE operation will appear to happen
447 before the RELEASE operation with respect to the other components of the
454 The use of ACQUIRE and RELEASE operations generally precludes the need
455 for other sorts of memory barrier (but note the exceptions mentioned in
456 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
474 Note that these are the _minimum_ guarantees. Different architectures may give
482 There are certain things that the Linux kernel memory barriers do not guarantee:
484 (*) There is no guarantee that any of the memory accesses specified before a
485 memory barrier will be _complete_ by the completion of a memory barrier
486 instruction; the barrier can be considered to draw a line in that CPU's
487 access queue that accesses of the appropriate type may not cross.
490 any direct effect on another CPU or any other hardware in the system. The
491 indirect effect will be the order in which the second CPU sees the effects
492 of the first CPU's accesses occur, but see the next point:
494 (*) There is no guarantee that a CPU will see the correct order of effects
495 from a second CPU's accesses, even _if_ the second CPU uses a memory
496 barrier, unless the first CPU _also_ uses a matching memory barrier (see
497 the subsection on "SMP Barrier Pairing").
499 (*) There is no guarantee that some intervening piece of off-the-CPU
500 hardware[*] will not reorder the memory accesses. CPU cache coherency
501 mechanisms should propagate the indirect effects of a memory barrier
515 it's not always obvious that they're needed. To illustrate, consider the
527 There's a clear data dependency here, and it would seem that by the end of the
534 leading to the following situation:
539 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
543 between the address load and the data load:
555 This enforces the occurrence of one of the two implications, and prevents the
560 even-numbered cache lines and the other bank processes odd-numbered cache
561 lines. The pointer P might be stored in an odd-numbered cache line, and the
562 variable B might be stored in an even-numbered cache line. Then, if the
563 even-numbered bank of the reading CPU's cache is extremely busy while the
564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
565 but the old value of the variable B (2).
569 number is read from memory and then used to calculate the index for an array
583 The data dependency barrier is very important to the RCU system,
585 include/linux/rcupdate.h. This permits the current target of an RCU'd
586 pointer to be replaced with a new modified target, without the replacement
589 See also the subsection on "Cache Coherency" for a more thorough example.
596 simply a data dependency barrier to make it work correctly. Consider the
605 This will not have the desired effect because there is no actual data
606 dependency, but rather a control dependency that the CPU may short-circuit
607 by attempting to predict the outcome in advance, so that other CPUs see
608 the load from b as having happened before the load from a. In such a
618 for load-store control dependencies, as in the following example:
626 said, please note that READ_ONCE() is not optional! Without the
627 READ_ONCE(), the compiler might combine the load from 'a' with other
628 loads from 'a', and the store to 'b' with other stores to 'b', with
631 Worse yet, if the compiler is able to prove (say) that the value of
633 to optimize the original example by eliminating the "if" statement
639 So don't leave out the READ_ONCE().
642 branches of the "if" statement as follows:
669 Now there is no conditional between the load from 'a' and the store to
670 'b', which means that the CPU is within its rights to reorder them:
671 The conditional is absolutely required, and must be present in the
686 ordering is guaranteed only when the stores differ, for example:
697 The initial READ_ONCE() is still required to prevent the compiler from
698 proving the value of 'a'.
700 In addition, you need to be careful what you do with the local variable 'q',
701 otherwise the compiler might be able to guess the value and again remove
702 the needed conditional. For example:
713 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
714 equal to zero, in which case the compiler is within its rights to
715 transform the above code into the following:
721 Given this transformation, the CPU is not required to respect the ordering
722 between the load from variable 'a' and the store to variable 'b'. It is
724 is gone, and the barrier won't bring it back. Therefore, if you are
738 Please note once again that the stores to 'b' differ. If they were
739 identical, as noted earlier, the compiler could pull this store outside
740 of the 'if' statement.
749 Because the first condition cannot fault and the second condition is
750 always true, the compiler can transform this example as following,
756 This example underscores the need to ensure that the compiler cannot
758 the compiler to actually emit code for a given load, it does not force
759 the compiler to use the results.
762 demonstrated by two related examples, with the initial values of
773 The above two-CPU example will never trigger the assert(). However,
775 then adding the following CPU would guarantee a related assertion:
783 But because control dependencies do -not- provide transitivity, the above
784 assertion can fail after the combined three-CPU example completes. If you
785 need the three-CPU example to provide ordering, you will need smp_mb()
786 between the loads and stores in the CPU 0 and CPU 1 code fragments,
787 that is, just before or just after the "if" statements. Furthermore,
788 the original two-CPU example is very fragile and should be avoided.
790 These two examples are the LB and WWC litmus tests from this paper:
800 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
803 (*) If both legs of the "if" statement begin with identical stores
804 to the same variable, a barrier() statement is required at the
805 beginning of each leg of the "if" statement.
808 between the prior load and the subsequent store, and this
809 conditional must involve the prior load. If the compiler is able
810 to optimize the conditional away, it will have also optimized
811 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
812 can help to preserve the needed conditional.
814 (*) Control dependencies require that the compiler avoid reordering the
817 Please see the Compiler Barrier section for more information.
871 Basically, the read barrier always has to be there, even though it can be of
872 the "weaker" type.
874 [!] Note that the stores before the write barrier would normally be expected to
875 match the loads after the read barrier or the data dependency barrier, and vice
891 Consider the following sequence of events:
902 This sequence of events is committed to the memory coherence system in an order
903 that the rest of the system might perceive as the unordered set of { STORE A,
904 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
911 | | : | A=1 | } \/ the rest of the system
915 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
916 | | +------+ } requires all stores prior to the
923 | Sequence in which stores are committed to the
929 loads. Consider the following sequence of events:
941 Without intervention, CPU 2 may perceive the events on CPU 1 in some
942 effectively random order, despite the write barrier issued by CPU 1:
965 up the maintenance \ +-------+ | |
971 In the above example, CPU 2 perceives that B is 7, despite the load of *C
972 (which would be B) coming after the LOAD of C.
974 If, however, a data dependency barrier were to be placed between the load of C
975 and the load of *C (ie: B) on CPU 2:
988 then the following will occur:
1009 prior to the store of C \ +-------+ | |
1015 And thirdly, a read barrier acts as a partial order on loads. Consider the
1027 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1028 some effectively random order, despite the write barrier issued by CPU 1:
1051 If, however, a read barrier were to be placed between the load of B and the
1064 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1080 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1082 prior to the storage of B ---->| A->1 |------>| |
1087 To illustrate this more completely, consider what could happen if the code
1088 contained a load of A either side of the read barrier:
1101 Even though the two loads of A both occur after the load of B, they may both
1120 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1122 prior to the storage of B ---->| A->1 |------>| 2nd |
1127 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1128 before the read barrier completes anyway:
1153 The guarantee is that the second load will always come up with A == 1 if the
1154 load of B came up with B == 2. No such guarantee exists for the first load of
1162 item from memory, and they find a time where they're not using the bus for any
1163 other loads, and so do the load in advance - even though they haven't actually
1164 got to that point in the instruction execution flow yet. This permits the
1165 actual load instruction to potentially complete immediately because the CPU
1166 already has the value to hand.
1168 It may turn out that the CPU didn't actually need the value - perhaps because a
1169 branch circumvented the load - in which case it can discard the value or just
1190 division speculates on the +-------+ ~ | |
1194 Once the divisions are complete --> : : ~-->| |
1195 the CPU can then perform the : : | |
1199 Placing a read barrier or a data dependency barrier just before the second
1211 dependent on the type of barrier used. If there was no change made to the
1212 speculated memory location, then the speculated value will just be used:
1221 division speculates on the +-------+ ~ | |
1234 the speculation will be cancelled and the value reloaded:
1243 division speculates on the +-------+ ~ | |
1277 CPU A follows a load from the same variable executing on CPU B, then
1278 CPU A's load must either return the same value that CPU B's load did,
1281 In the Linux kernel, use of general memory barriers guarantees
1282 transitivity. Therefore, in the above example, if CPU 2's load from X
1287 For example, suppose that CPU 2's general barrier in the above example
1306 on the combined order of CPU 1's and CPU 2's accesses.
1329 The Linux kernel has an explicit compiler barrier function that prevents the
1330 compiler from moving the memory accesses either side of it to the other side:
1336 thought of as weak forms of barrier() that affect only the specific
1337 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1339 The barrier() function has the following effects:
1341 (*) Prevents the compiler from reordering accesses following the
1342 barrier() to precede any accesses preceding the barrier().
1344 interrupt-handler code and the code that was interrupted.
1346 (*) Within a loop, forces the compiler to load the variables used
1355 to the same variable, and in some cases, the CPU is within its
1356 rights to reorder loads to the same variable. This means that
1357 the following code:
1363 Prevent both the compiler and the CPU from doing this as follows:
1372 the same variable. Such merging can cause the compiler to "optimize"
1373 the following code:
1378 into the following code, which, although in some sense legitimate
1379 for single-threaded code, is almost certainly not what the developer
1386 Use READ_ONCE() to prevent the compiler from doing this to you:
1392 in cases where high register pressure prevents the compiler from
1394 therefore optimize the variable 'tmp' out of our previous example:
1399 This could result in the following code, which is perfectly safe in
1405 For example, the optimized version of this code could result in
1406 passing a zero to do_something_with() in the case where the variable
1407 a was modified by some other CPU between the "while" statement and
1408 the call to do_something_with().
1410 Again, use READ_ONCE() to prevent the compiler from doing this:
1415 Note that if the compiler runs short of registers, it might save
1416 tmp onto the stack. The overhead of this saving and later restoring
1418 single-threaded code, so you need to tell the compiler about cases
1422 what the value will be. For example, if the compiler can prove that
1423 the value of variable 'a' is always zero, it can optimize this code:
1433 gets rid of a load and a branch. The problem is that the compiler
1434 will carry out its proof assuming that the current CPU is the only
1435 one updating variable 'a'. If variable 'a' is shared, then the
1436 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1442 But please note that the compiler is also closely watching what you
1443 do with the value after the READ_ONCE(). For example, suppose you
1444 do the following and MAX is a preprocessor macro with the value 1:
1449 Then the compiler knows that the result of the "%" operator applied
1450 to MAX will always be zero, again allowing the compiler to optimize
1451 the code into near-nonexistence. (It will still load from the
1454 (*) Similarly, the compiler is within its rights to omit a store entirely
1455 if it knows that the variable already has the value being stored.
1456 Again, the compiler assumes that the current CPU is the only one
1457 storing into the variable, which can cause the compiler to do the
1459 the following:
1465 The compiler sees that the value of variable 'a' is already zero, so
1466 it might well omit the second store. This would come as a fatal
1467 surprise if some other CPU might have stored to variable 'a' in the
1470 Use WRITE_ONCE() to prevent the compiler from making this sort of
1478 you tell it not to. For example, consider the following interaction
1493 There is nothing to prevent the compiler from transforming
1494 process_level() to the following, in fact, this might well be a
1503 If the interrupt occurs between these two statement, then
1519 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1529 You should assume that the compiler can move READ_ONCE() and
1535 WRITE_ONCE(), the compiler need only forget the contents of the
1536 indicated memory locations, while with barrier() the compiler must
1537 discard the value of all memory locations that it has currented
1538 cached in any machine registers. Of course, the compiler must also
1539 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1540 though the CPU of course need not do so.
1543 as in the following example:
1576 16-bit store instructions with 7-bit immediate fields, the compiler
1578 implement the following 32-bit store:
1584 than two instructions to build the constant and then store it.
1587 this optimization in a volatile store. In the absence of such bugs,
1588 use of WRITE_ONCE() prevents store tearing in the following example:
1608 volatile markings, the compiler would be well within its rights to
1625 Please note that these compiler barriers have no direct effect on the CPU,
1642 All memory barriers except the data dependency barriers imply a compiler
1645 Aside: In the case of data dependencies, the compiler would be expected
1646 to issue the loads in the correct order (eg. `a[b]` would have to load
1647 the value of b before loading a[b]), however there is no guarantee in
1648 the C specification that the compiler may not speculate the value of b
1650 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1652 has not yet been reached about these problems, however the READ_ONCE()
1659 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1660 references to shared memory on SMP systems, though the use of locking instead
1666 These are required even on non-SMP systems as they affect the order in which
1667 memory operations appear to a device by prohibiting both the compiler and the
1675 This assigns the value to the variable and then inserts a full memory
1676 barrier after it, depending on the function. It isn't guaranteed to
1691 and then decrements the object's reference count:
1697 This makes sure that the death mark on the object is perceived to be set
1698 *before* the reference counter is decremented.
1700 See Documentation/atomic_ops.txt for more information. See the "Atomic
1705 This can be thought of as a pointer-fetch wrapper around the
1710 example, when the objects removed only when the system goes down.
1718 These are for use with consistent memory to guarantee the ordering
1719 of writes or reads of shared memory accessible to both the CPU and a
1723 and uses a descriptor status value to indicate if the descriptor belongs
1724 to the device or the CPU, and a doorbell to notify it when new
1748 The dma_rmb() allows us guarantee the device has released ownership
1749 before we read the data from the descriptor, and the dma_wmb() allows
1750 us to guarantee the data is written to the descriptor before the device
1751 can see it now has ownership. The wmb() is needed to guarantee that the
1753 the cache incoherent MMIO region.
1765 This is a variation on the mandatory write barrier that causes writes to weakly
1766 ordered I/O regions to be partially ordered. Its effects may go beyond the
1767 CPU->Hardware interface and actually affect the hardware at some level.
1769 See the subsection "Locks vs I/O accesses" for more information.
1776 Some of the other functions in the linux kernel imply memory barriers, amongst
1800 Memory operations issued after the ACQUIRE will be completed after the
1803 Memory operations issued before the ACQUIRE may be completed after
1804 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1811 Memory operations issued before the RELEASE will be completed before the
1814 Memory operations issued after the RELEASE may be completed before the
1825 completed before the RELEASE operation.
1829 Certain locking variants of the ACQUIRE operation may fail, either due to
1830 being unable to get the lock immediately, or due to receiving an unblocked
1831 signal whilst asleep waiting for the lock to become available. Failed
1834 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1835 one-way barriers is that the effects of instructions outside of a critical
1836 section may seep into the inside of the critical section.
1839 because it is possible for an access preceding the ACQUIRE to happen after the
1840 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1841 the two accesses can themselves then cross:
1852 When the ACQUIRE and RELEASE are a lock acquisition and release,
1853 respectively, this same reordering can occur if the lock's ACQUIRE and
1854 RELEASE are to the same lock variable, but only from the perspective of
1858 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
1859 not imply a full memory barrier. Therefore, the CPU's execution of the
1860 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
1874 the RELEASE would simply complete, thereby avoiding the deadlock.
1878 One key point is that we are only talking about the CPU doing
1879 the reordering, not the compiler. If the compiler (or, for
1880 that matter, the developer) switched the operations, deadlock
1883 But suppose the CPU reordered the operations. In this case,
1884 the unlock precedes the lock in the assembly code. The CPU
1885 simply elected to try executing the later lock operation first.
1888 execute the unlock operation (which preceded the lock operation
1889 in the assembly code), which will unravel the potential deadlock,
1890 allowing the lock operation to succeed.
1892 But what if the lock is a sleeplock? In that case, the code will
1893 try to enter the scheduler, where it will eventually encounter
1894 a memory barrier, which will force the earlier unlock operation
1895 to complete, again unraveling the deadlock. There might be
1896 a sleep-unlock race, but the locking primitive needs to resolve
1904 See also the section on "Inter-CPU locking barrier effects".
1907 As an example, consider the following:
1924 But none of the following are:
1946 interaction between two pieces of data: the task state of the task waiting for
1947 the event and the global data used to indicate the event. To make sure that
1948 these appear to happen in the right order, the primitives to begin the process
1949 of going to sleep, and the primitives to initiate a wake up imply certain
1952 Firstly, the sleeper normally follows something like this sequence of events:
1962 after it has altered the task state:
1977 which therefore also imply a general memory barrier after setting the state.
1979 interpolate the memory barrier in the right place:
2002 something up. The barrier occurs before the task state is cleared, and so sits
2003 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2014 is actually awakened. To see this, consider the following sequence of
2047 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2048 order multiple stores before the wake-up with respect to loads of those stored
2049 values after the sleeper has called set_current_state(). For instance, if the
2058 and the waker does:
2064 there's no guarantee that the change to event_indicated will be perceived by
2065 the sleeper as coming after the change to my_data. In such a circumstance, the
2066 code on both sides must interpolate its own memory barriers between the
2067 separate data accesses. Thus the above sleeper ought to do:
2075 and the waker should do:
2096 that does affect memory access ordering on other CPUs, within the context of
2103 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2104 three CPUs; then should the following sequence of events occur:
2115 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2116 through *H occur in, other than the constraints imposed by the separate locks
2117 on the separate CPUs. It might, for example, see:
2134 two spinlocked sections on two different CPUs may be seen as interleaved by the
2135 PCI bridge, because the PCI bridge does not necessarily participate in the
2136 cache-coherence protocol, and is therefore incapable of issuing the required
2152 may be seen by the PCI bridge as follows:
2156 which would probably cause the hardware to malfunction.
2159 What is necessary here is to intervene with an mmiowb() before dropping the
2175 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2176 before either of the stores issued on CPU 2.
2179 Furthermore, following a store by a load from the same device obviates the need
2180 for the mmiowb(), because the load forces the store to complete before the load
2219 When there's a system with more than one processor, more than one CPU in the
2220 system may be working on the same data set at the same time. This can cause
2221 synchronisation problems, and the usual way of dealing with them is to use
2223 operate without the use of a lock if at all possible. In such a case
2227 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2228 queued on the semaphore, by virtue of it having a piece of its stack linked to
2229 the semaphore's list of waiting processes:
2242 To wake up a particular waiter, the up_read() or up_write() functions have to:
2244 (1) read the next pointer from this waiter's record to know as to where the
2247 (2) read the pointer to the waiter's task structure;
2249 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2251 (4) call wake_up_process() on the task; and
2253 (5) release the reference held on the waiter's task struct.
2263 and if any of these steps occur out of order, then the whole thing may
2266 Once it has queued itself and dropped the semaphore lock, the waiter does not
2267 get the lock again; it instead just waits for its task pointer to be cleared
2268 before proceeding. Since the record is on the waiter's stack, this means that
2269 if the task pointer is cleared _before_ the next pointer in the list is read,
2270 another CPU might start processing the waiter and might clobber the waiter's
2271 stack before the up*() function has a chance to read the next pointer.
2273 Consider then what might happen to the above sequence of events:
2293 This could be dealt with using the semaphore lock, but then the down_xxx()
2294 function has to needlessly get the spinlock again after being woken up.
2305 In this case, the barrier makes a guarantee that all memory accesses before the
2306 barrier will appear to happen before all the memory accesses after the barrier
2307 with respect to the other CPUs on the system. It does _not_ guarantee that all
2308 the memory accesses before the barrier will be complete by the time the barrier
2311 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2312 compiler barrier, thus making sure the compiler emits the instructions in the
2313 right order without actually intervening in the CPU. Since there's only one
2322 some don't, but they're very heavily relied on as a group throughout the
2326 about the state (old or new) implies an SMP-conditional general memory barrier
2327 (smp_mb()) on each side of the actual operation (with the exception of
2351 such the implicit memory barrier effects are necessary.
2363 With these the appropriate explicit memory barrier should be used if necessary
2380 they probably don't need memory barriers because either the reference count
2381 will be adjusted inside a locked section, or the caller will already hold
2382 sufficient references to make the lock, and thus a memory barrier unnecessary.
2402 situations because on some CPUs the atomic instructions used imply full memory
2404 and in such cases the special barrier primitives will be no-ops.
2412 Many devices can be memory mapped, and so appear to the CPU as if they're just
2413 a set of memory locations. To control such a device, the driver usually has to
2414 make the right memory accesses in exactly the right order.
2417 in that the carefully sequenced accesses in the driver code won't reach the
2418 device in the requisite order if the CPU or the compiler thinks it is more
2420 the device to malfunction.
2422 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2424 appropriately sequential. Whilst this, for the most part, renders the explicit
2430 issued prior to unlocking the critical section.
2432 (2) If the accessor functions are used to refer to an I/O memory window with
2442 A driver may be interrupted by its own interrupt service routine, and thus the
2443 two parts of the driver may interfere with each other's attempts to control or
2444 access the device.
2447 form of locking), such that the critical operations are all contained within
2448 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2449 routine is executing, the driver's core may not run on the same CPU, and its
2450 interrupt is not permitted to happen again until the current interrupt has been
2451 handled, thus the interrupt handler does not need to lock against that.
2454 address register and a data register. If that driver's core talks to the card
2455 under interrupt-disablement and then the driver's interrupt handler is invoked:
2466 The store to the data register might happen after the second store to the
2477 Normally this won't be a problem because the I/O accesses done inside such
2492 When accessing I/O memory, drivers should use the appropriate accessor
2503 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2504 space. However, it may also be mapped as a virtual I/O space in the CPU's
2509 intermediary bridges (such as the PCI host bridge) may not fully honour
2520 respect to each other on the issuing CPU depends on the characteristics
2521 defined for the memory window through which they're accessing. On later
2522 i386 architecture machines, for example, this is controlled by way of the
2529 deferral if it so wishes; to flush a store, a load from the same location
2530 is preferred[*], but a load from the same device or from configuration
2533 [*] NOTE! attempting to load from the same location as was written to may
2534 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2540 Please refer to the PCI specification for more information on interactions
2548 ordering with respect to LOCK or UNLOCK operations. If the latter is
2550 the same peripheral are guaranteed to be ordered with respect to each
2555 These will perform appropriately for the type of access they're actually
2563 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2564 maintain the appearance of program causality with respect to itself. Some CPUs
2566 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2569 This means that it must be considered that the CPU will execute its instruction
2571 instruction in the stream depends on an earlier instruction, then that
2572 earlier instruction must be sufficiently complete[*] before the later
2573 instruction may proceed; in other words: provided that the appearance of
2576 [*] Some instructions have more than one effect - such as changing the
2582 immediate value into the same register, the first may be discarded.
2585 Similarly, it has to be assumed that compiler might reorder the instruction
2586 stream in any way it sees fit, again provided the appearance of causality is
2594 The way cached memory operations are perceived across the system is affected to
2595 a certain extent by the caches that lie between CPUs and memory, and by the
2596 memory coherence system that maintains the consistency of state in the system.
2598 As far as the way a CPU interacts with another part of the system through the
2599 caches goes, the memory system has to include the CPU's caches, and memory
2600 barriers for the most part act at the interface between the CPU and its cache
2601 (memory barriers logically act on the dotted line in the following diagram):
2625 Although any particular load or store may not actually appear outside of the
2626 CPU that issued it since it may have been satisfied within the CPU's own cache,
2627 it will still appear as if the full memory access had taken place as far as the
2628 other CPUs are concerned since the cache coherency mechanisms will migrate the
2629 cacheline over to the accessing CPU and propagate the effects upon conflict.
2631 The CPU core may execute instructions in any order it deems fit, provided the
2632 expected program causality appears to be maintained. Some of the instructions
2633 generate load and store operations which then go into the queue of memory
2634 accesses to be performed. The core may place these in the queue in any order
2638 What memory barriers are concerned with is controlling the order in which
2639 accesses cross from the CPU side of things to the memory side of things, and
2640 the order in which the effects are perceived to happen by the other observers
2641 in the system.
2646 [!] MMIO or other device accesses may bypass the cache system. This depends on
2647 the properties of the memory window through which devices are accessed and/or
2648 the use of any special device communication instructions the CPU may have.
2654 Life isn't quite as simple as it may appear above, however: for while the
2658 become apparent in the same order on those other CPUs.
2684 Imagine the system has the following properties:
2692 (*) whilst the CPU core is interrogating one cache, the other cache may be
2693 making use of the bus to access the rest of the system - perhaps to
2697 to maintain coherency with the rest of the system;
2699 (*) the coherency queue is not flushed by normal loads to lines already
2700 present in the cache, even though the contents of the queue may
2703 Imagine, then, that two writes are made on the first CPU, with a write barrier
2705 the requisite order:
2717 The write memory barrier forces the other CPUs in the system to perceive that
2718 the local CPU's caches have apparently been updated in the correct order. But
2719 now imagine that the second CPU wants to read those values:
2727 The above pair of reads may then fail to happen in the expected order, as the
2728 cacheline holding p may get updated in one of the second CPU's caches whilst
2729 the update to the cacheline holding v is delayed in the other of the second
2749 no guarantee that, without intervention, the order of update will be the same
2754 barrier between the loads. This will force the cache to commit its coherency
2776 split cache that improves performance by making better use of the data bus.
2777 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2780 Other CPUs may also have split caches, but must coordinate between the various
2781 cachelets for normal memory accesses. The semantics of the Alpha removes the
2782 need for coordination in the absence of memory barriers.
2790 dirty cache lines may be resident in the caches of various CPUs, and may not
2791 have been written back to RAM yet. To deal with this, the appropriate part of
2792 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2795 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2796 cache lines being written back to RAM from a CPU's cache after the device has
2797 installed its own data, or cache lines present in the CPU's cache may simply
2798 obscure the fact that RAM has been updated, until at such time as the cacheline
2799 is discarded from the CPU's cache and reloaded. To deal with this, the
2800 appropriate part of the kernel must invalidate the overlapping bits of the
2810 a window in the CPU's memory space that has different properties assigned than
2811 the usual RAM directed window.
2813 Amongst these properties is usually the fact that such accesses bypass the
2814 caching entirely and go directly to the device buses. This means MMIO accesses
2816 A memory barrier isn't sufficient in such a case, but rather the cache must be
2817 flushed between the cached memory write and the MMIO access if the two are in
2825 A programmer might take it for granted that the CPU will perform memory
2826 operations in exactly the order specified, so that if the CPU is, for example,
2827 given the following piece of code to execute:
2835 they would then expect that the CPU will complete the memory operation for each
2836 instruction before moving on to the next one, leading to a definite sequence of
2837 operations as seen by external observers in the system:
2842 Reality is, of course, much messier. With many CPUs and compilers, the above
2849 (*) loads may be done speculatively, and the result discarded should it prove
2852 (*) loads may be done speculatively, leading to the result having been fetched
2853 at the wrong time in the expected sequence of events;
2855 (*) the order of the memory accesses may be rearranged to promote better use
2856 of the CPU buses and caches;
2863 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2864 mechanisms may alleviate this - once the store has actually hit the cache
2865 - there's no guarantee that the coherency management will be propagated in
2868 So what another CPU, say, might actually observe from the above piece of code
2877 _own_ accesses appear to be correctly ordered, without the need for a memory
2878 barrier. For instance with the following code:
2888 the final result will appear to be:
2890 U == the original value of *A
2895 The code above may cause the CPU to generate the full sequence of memory
2900 in that order, but, without intervention, the sequence may have almost any
2901 combination of elements combined or discarded, provided the program's view
2902 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2903 are -not- optional in the above example, as there are architectures
2904 where a given CPU might reorder successive loads to the same location.
2906 necessary to prevent this, for example, on Itanium the volatile casts
2907 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2910 The compiler may also combine, discard or defer elements of the sequence before
2911 the CPU even sees them.
2923 assumed that the effect of the storage of V to *A is lost. Similarly:
2934 and the LOAD operation never appear outside of the CPU.
2940 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2941 some versions of the Alpha CPU have a split data cache, permitting them to have
2943 the data dependency barrier really becomes necessary as this synchronises both
2944 caches with the memory coherence system, thus making it seem like pointer
2945 changes vs new data occur in the right order.
2947 The Alpha defines the Linux kernel's memory barrier model.
2949 See the subsection on "Cache Coherency" above.
2959 Memory barriers can be used to implement circular buffering without the need
2960 of a lock to serialise the producer with the consumer. See:
2990 Appendix D: Formal Specification of the Memory Models
2991 Appendix J: Programming with the Memory Models
3005 Appendix D: Formal Specifications of the Memory Models
3007 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005