Lines Matching refs:sequence

113 For example, consider the following sequence of events:
147 As a further example, consider this sequence of events:
156 the address retrieved from P by CPU 2.  At the end of the sequence, any of the
214      the CPU will only issue the following sequence of memory operations:
298 		either an object of scalar type, or a maximal sequence
352      A CPU can be viewed as committing a sequence of store operations to the
354      occur in the sequence _before_ all the stores after the write barrier.
377      load touches one of a sequence of stores from another CPU, then by the
516 following sequence of events:
528 sequence, Q must be either &A or &B, and that:
891 Consider the following sequence of events:
902 This sequence of events is committed to the memory coherence system in an order
929 loads.  Consider the following sequence of events:
1016 following sequence of events:
1918 The following sequence of events is acceptable:
1952 Firstly, the sleeper normally follows something like this sequence of events:
1978 The whole sequence above is available in various canned forms, all of which
2014 is actually awakened.  To see this, consider the following sequence of
2104 three CPUs; then should the following sequence of events occur:
2255 In other words, it has to perform this sequence of events:
2273 Consider then what might happen to the above sequence of events:
2580 A CPU may also discard any instruction sequence that winds up having no
2836 instruction before moving on to the next one, leading to a definite sequence of
2853      at the wrong time in the expected sequence of events;
2895 The code above may cause the CPU to generate the full sequence of memory
2900 in that order, but, without intervention, the sequence may have almost any
2910 The compiler may also combine, discard or defer elements of the sequence before