Lines Matching refs:pair

457      pair is -not- guaranteed to act as a full memory barrier.  However, after
625 Control dependencies pair normally with other types of barriers.  That
819   (*) Control dependencies pair normally with other types of barriers.
831 General barriers pair with each other, though they also pair with most
833 pairs with a release barrier, but both may also pair with other barriers,
1301 The key point is that although CPU 2's read barrier orders its pair
1609      implement these three assignment statements as a pair of 32-bit
1610      loads followed by a pair of 32-bit stores.  This would result in
2103 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2661 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2727 The above pair of reads may then fail to happen in the expected order, as the