Lines Matching refs:ordering

53  (*) Assumed minimum execution ordering model.
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
327 ordering over the memory operations on either side of the barrier.
349      A write barrier is a partial ordering on stores only; it is not required
369      A data dependency barrier is a partial ordering on interdependent loads
383      showing the ordering constraints.
403      A read barrier is a partial ordering on loads only; it is not required to
420      A general memory barrier is a partial ordering over both loads and stores.
617 However, stores are not speculated.  This means that ordering -is- provided
629 possible highly counterintuitive effects on ordering.
641 It is tempting to try to enforce ordering on identical stores on both
660 	WRITE_ONCE(b, p);  /* BUG: No ordering vs. load from a!!! */
673 Therefore, if you need ordering in this example, you need explicit
686 ordering is guaranteed only when the stores differ, for example:
721 Given this transformation, the CPU is not required to respect the ordering
725 relying on this ordering, you should make sure that MAX is greater than
785 need the three-CPU example to provide ordering, you will need smp_mb()
797       However, they do -not- guarantee any other sort of ordering:
799       later anything.  If you need these other forms of ordering,
811       away the ordering.  Careful use of READ_ONCE() and WRITE_ONCE()
1064 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1258 Transitivity is a deeply intuitive notion about ordering that is not
1643 barrier. Data dependencies do not impose any additional compiler ordering.
1659 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1718      These are for use with consistent memory to guarantee the ordering
1899 Locks and semaphores may not provide any guarantee of ordering on UP compiled
2096 that does affect memory access ordering on other CPUs, within the context of
2314 CPU, that CPU's dependency ordering logic will take care of everything else.
2434      required to enforce ordering.
2467 address register if ordering rules are sufficiently relaxed:
2472 If ordering rules are relaxed, it must be assumed that accesses done inside an
2485 likely, then interrupt-disabling locks should be used to guarantee ordering.
2546      ordering guarantees. Specifically, they do not guarantee ordering with
2548      ordering with respect to LOCK or UNLOCK operations. If the latter is
2863  (*) the CPU's data cache may affect the ordering, and whilst cache-coherency