Lines Matching refs:may
18 - What may not be assumed about memory barriers?
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
104 appears to be maintained. Similarly, the compiler may also arrange the
142 Furthermore, the stores committed by a CPU to the memory system may not be
192 There are some minimal guarantees that may be expected of a CPU:
242 we may get any of the following sequences:
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
256 we may get any one of the following sequences:
266 we may get any of:
436 Memory operations that occur before an ACQUIRE operation may appear to
451 Memory operations that occur after a RELEASE operation may appear to
474 Note that these are the _minimum_ guarantees. Different architectures may give
475 more substantial guarantees, but they may _not_ be relied upon outside of arch
487 access queue that accesses of the appropriate type may not cross.
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
538 Whilst this may seem like a failure of coherency or causality maintenance, it
606 dependency, but rather a control dependency that the CPU may short-circuit
833 pairs with a release barrier, but both may also pair with other barriers,
918 | | : +------+ } further stores may take place
941 Without intervention, CPU 2 may perceive the events on CPU 1 in some
1027 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1101 Even though the two loads of A both occur after the load of B, they may both
1127 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1155 A; that may come up with either A == 0 or A == 1.
1168 It may turn out that the CPU didn't actually need the value - perhaps because a
1626 which may then reorder things however it wishes.
1648 the C specification that the compiler may not speculate the value of b
1664 barriers unnecessarily impose overhead on UP systems. They may, however, be
1766 ordered I/O regions to be partially ordered. Its effects may go beyond the
1779 This specification is a _minimum_ guarantee; any particular architecture may
1780 provide more substantial guarantees, but these may not be relied upon outside
1803 Memory operations issued before the ACQUIRE may be completed after
1814 Memory operations issued after the RELEASE may be completed before the
1829 Certain locking variants of the ACQUIRE operation may fail, either due to
1836 section may seep into the inside of the critical section.
1838 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1848 may occur as:
1856 RELEASE may -not- be assumed to be a full memory barrier.
1899 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1972 set_current_state() may be wrapped by:
2134 two spinlocked sections on two different CPUs may be seen as interleaved by the
2152 may be seen by the PCI bridge as follows:
2220 system may be working on the same data set at the same time. This can cause
2222 locks. Locks, however, are quite expensive, and so it may be preferable to
2224 operations that affect both CPUs may have to be carefully ordered to prevent
2263 and if any of these steps occur out of order, then the whole thing may
2367 The following also do _not_ imply memory barriers, and so may require explicit
2442 A driver may be interrupted by its own interrupt service routine, and thus the
2443 two parts of the driver may interfere with each other's attempts to control or
2446 This may be alleviated - at least in part - by disabling local interrupts (a
2449 routine is executing, the driver's core may not run on the same CPU, and its
2473 interrupt disabled section may leak outside of it and may interleave with
2480 mmiowb() may need to be used explicitly.
2483 A similar situation may occur between an interrupt routine and two routines
2504 space. However, it may also be mapped as a virtual I/O space in the CPU's
2508 Accesses to this space may be fully synchronous (as on i386), but
2509 intermediary bridges (such as the PCI host bridge) may not fully honour
2528 However, intermediary hardware (such as a PCI bridge) may indulge in
2533 [*] NOTE! attempting to load from the same location as was written to may
2537 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2573 instruction may proceed; in other words: provided that the appearance of
2578 instructions may depend on different effects.
2580 A CPU may also discard any instruction sequence that winds up having no
2582 immediate value into the same register, the first may be discarded.
2625 Although any particular load or store may not actually appear outside of the
2626 CPU that issued it since it may have been satisfied within the CPU's own cache,
2631 The CPU core may execute instructions in any order it deems fit, provided the
2634 accesses to be performed. The core may place these in the queue in any order
2646 [!] MMIO or other device accesses may bypass the cache system. This depends on
2648 the use of any special device communication instructions the CPU may have.
2654 Life isn't quite as simple as it may appear above, however: for while the
2686 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2689 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2692 (*) whilst the CPU core is interrogating one cache, the other cache may be
2700 present in the cache, even though the contents of the queue may
2727 The above pair of reads may then fail to happen in the expected order, as the
2728 cacheline holding p may get updated in one of the second CPU's caches whilst
2778 access depends on a read, not all do, so it may not be relied on.
2780 Other CPUs may also have split caches, but must coordinate between the various
2789 such cases, a device attempting DMA may obtain stale data from RAM because
2790 dirty cache lines may be resident in the caches of various CPUs, and may not
2795 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2797 installed its own data, or cache lines present in the CPU's cache may simply
2815 may, in effect, overtake accesses to cached memory that were emitted earlier.
2849 (*) loads may be done speculatively, and the result discarded should it prove
2852 (*) loads may be done speculatively, leading to the result having been fetched
2855 (*) the order of the memory accesses may be rearranged to promote better use
2858 (*) loads and stores may be combined to improve performance when talking to
2860 thus cutting down on transaction setup costs (memory and PCI devices may
2863 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2864 mechanisms may alleviate this - once the store has actually hit the cache
2895 The code above may cause the CPU to generate the full sequence of memory
2900 in that order, but, without intervention, the sequence may have almost any
2910 The compiler may also combine, discard or defer elements of the sequence before
2918 may be reduced to:
2928 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be