Lines Matching refs:instruction

486      instruction; the barrier can be considered to draw a line in that CPU's
1164 got to that point in the instruction execution flow yet.  This permits the
1165 actual load instruction to potentially complete immediately because the CPU
1573      with a single memory-reference instruction, prevents "load tearing"
2309 instruction itself is complete.
2569 This means that it must be considered that the CPU will execute its instruction
2571 instruction in the stream depends on an earlier instruction, then that
2572 earlier instruction must be sufficiently complete[*] before the later
2573 instruction may proceed; in other words: provided that the appearance of
2580 A CPU may also discard any instruction sequence that winds up having no
2585 Similarly, it has to be assumed that compiler might reorder the instruction
2635 it wishes, and continue execution until it is forced to wait for an instruction
2836 instruction before moving on to the next one, leading to a definite sequence of