Lines Matching refs:example
113 For example, consider the following sequence of events:
147 As a further example, consider this sequence of events:
293 using older pre-C11 compilers (for example, gcc 4.6). The portion
559 machines with split caches, so that, for example, one cache bank processes
568 Another example of where data dependency barriers might be required is where a
584 for example. See rcu_assign_pointer() and rcu_dereference() in
589 See also the subsection on "Cache Coherency" for a more thorough example.
618 for load-store control dependencies, as in the following example:
633 to optimize the original example by eliminating the "if" statement
673 Therefore, if you need ordering in this example, you need explicit
674 memory barriers, for example, smp_store_release():
686 ordering is guaranteed only when the stores differ, for example:
702 the needed conditional. For example:
743 evaluation. Consider this example:
750 always true, the compiler can transform this example as following,
756 This example underscores the need to ensure that the compiler cannot
773 The above two-CPU example will never trigger the assert(). However,
784 assertion can fail after the combined three-CPU example completes. If you
785 need the three-CPU example to provide ordering, you will need smp_mb()
788 the original two-CPU example is very fragile and should be avoided.
971 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1259 always provided by real computer systems. The following example
1276 This expectation is an example of transitivity: if a load executing on
1282 transitivity. Therefore, in the above example, if CPU 2's load from X
1287 For example, suppose that CPU 2's general barrier in the above example
1297 This substitution destroys transitivity: in this example, it is perfectly
1303 this example runs on a system where CPUs 1 and 2 share a store buffer
1343 One example use for this property is to ease communication between
1391 (*) The compiler is within its rights to reload a variable, for example,
1394 therefore optimize the variable 'tmp' out of our previous example:
1405 For example, the optimized version of this code could result in
1422 what the value will be. For example, if the compiler can prove that
1443 do with the value after the READ_ONCE(). For example, suppose you
1458 wrong thing for shared variables. For example, suppose you have
1478 you tell it not to. For example, consider the following interaction
1522 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1543 as in the following example:
1575 multiple smaller accesses. For example, given an architecture having
1588 use of WRITE_ONCE() prevents store tearing in the following example:
1593 as in this example:
1612 and WRITE_ONCE() again prevent tearing in this example:
1619 WRITE_ONCE() on a variable that has been marked volatile. For example,
1690 As an example, consider a piece of code that marks an object as being dead
1710 example, when the objects removed only when the system goes down.
1722 For example, consider a device driver that shares memory with a device
1907 As an example, consider the following:
2117 on the separate CPUs. It might, for example, see:
2139 For example:
2160 spinlock, for example:
2227 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2522 i386 architecture machines, for example, this is controlled by way of the
2535 example.
2581 ultimate effect. For example, if two adjacent instructions both load an
2826 operations in exactly the order specified, so that if the CPU is, for example,
2903 are -not- optional in the above example, as there are architectures
2906 necessary to prevent this, for example, on Itanium the volatile casts