Lines Matching refs:dependency

19      - Data dependency barriers.
155 There is an obvious data dependency here, as the value loaded into D depends on
357      dependency barriers; see the "SMP barrier pairing" subsection.
360  (2) Data dependency barriers.
362      A data dependency barrier is a weaker form of read barrier.  In the case
365      load will be directed), a data dependency barrier would be required to
369      A data dependency barrier is a partial ordering on interdependent loads
375      considered can then perceive.  A data dependency barrier issued by the CPU
380      dependency barrier.
385      [!] Note that the first load really has to have a _data_ dependency and
386      not a control dependency.  If the address for the second load is dependent
387      on the first load, but the dependency is through a conditional rather than
388      actually loading the address itself, then it's a _control_ dependency and
392      [!] Note that data dependency barriers should normally be paired with
398      A read barrier is a data dependency barrier plus a guarantee that all the
406      Read memory barriers imply data dependency barriers, and so can substitute
514 The usage requirements of data dependency barriers are a little subtle, and
527 There's a clear data dependency here, and it would seem that by the end of the
542 To deal with this, a data dependency barrier or better must be inserted
552 			      <data dependency barrier>
568 Another example of where data dependency barriers might be required is where a
579 			      <data dependency barrier>
583 The data dependency barrier is very important to the RCU system,
595 A load-load control dependency requires a full read memory barrier, not
596 simply a data dependency barrier to make it work correctly.  Consider the
601 		<data dependency barrier>  /* BUG: No data dependency!!! */
606 dependency, but rather a control dependency that the CPU may short-circuit
751 defeating control dependency:
815       dependency into nonexistence.  Careful use of READ_ONCE() or
816       atomic{,64}_read() can help to preserve your control dependency.
835 dependency barrier, a control dependency, an acquire barrier, a release
837 control dependency, or a data dependency barrier pairs with a write
855 			      <data dependency barrier>
865 			         <implicit control dependency>
875 match the loads after the read barrier or the data dependency barrier, and vice
928 Secondly, data dependency barriers act as partial orderings on data-dependent
974 If, however, a data dependency barrier were to be placed between the load of C
985 				<data dependency barrier>
1199 Placing a read barrier or a data dependency barrier just before the second
1642 All memory barriers except the data dependency barriers imply a compiler
1706      smp_read_barrier_depends() data-dependency barrier.
2314 CPU, that CPU's dependency ordering logic will take care of everything else.
2753 To intervene, we need to interpolate a data dependency barrier or a read
2777 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2943 the data dependency barrier really becomes necessary as this synchronises both