Lines Matching refs:Memory
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
326 Memory barriers are such interventions. They impose a perceived partial
332 branch prediction and various types of caching. Memory barriers are used to
340 Memory barriers come in four basic varieties:
436 Memory operations that occur before an ACQUIRE operation may appear to
451 Memory operations that occur after a RELEASE operation may appear to
468 Memory barriers are only required where there's a possibility of interaction
1800 Memory operations issued after the ACQUIRE will be completed after the
1803 Memory operations issued before the ACQUIRE may be completed after
1811 Memory operations issued before the RELEASE will be completed before the
1814 Memory operations issued after the RELEASE may be completed before the
2603 <--- CPU ---> : <----------- Memory ----------->
2607 | CPU | | Memory | : | CPU | | | | |
2609 | | | Queue | : | | | |--->| Memory |
2617 | CPU | | Memory | : | CPU | | |--->| Device |
2643 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2673 : | Memory |
2809 Memory mapped I/O usually takes place through memory locations that are part of
2959 Memory barriers can be used to implement circular buffering without the need
2979 Chapter 7.1: Memory-Access Ordering
2980 Chapter 7.4: Buffering and Combining Memory Writes
2985 Chapter 7.2: Memory Ordering
2989 Chapter 8: Memory Models
2990 Appendix D: Formal Specification of the Memory Models
2991 Appendix J: Programming with the Memory Models
2994 Chapter 5: Memory Accesses and Cacheability
2995 Chapter 15: Sparc-V9 Memory Models
2998 Chapter 9: Memory Models
3001 Chapter 8: Memory Models
3004 Chapter 9: Memory
3005 Appendix D: Formal Specifications of the Memory Models
3008 Chapter 8: Memory Models
3017 Chapter 13: Other Memory Models
3021 Section 4.4: Memory Access