Lines Matching refs:B
117 { A == 1; B == 2 }
118 A = 3; x = B;
119 B = 4; y = A;
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
131 STORE B=4, ...
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
152 B = 4; Q = P;
153 P = &B D = *Q;
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
240 X = *A; Y = *B; *D = Z;
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
521 B = 4;
523 WRITE_ONCE(P, &B)
528 sequence, Q must be either &A or &B, and that:
531 (Q == &B) implies (D == 4)
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
536 (Q == &B) and (D == 2) ????
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
548 B = 4;
550 WRITE_ONCE(P, &B);
562 variable B might be stored in an even-numbered cache line. Then, if the
564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
565 but the old value of the variable B (2).
896 STORE B = 2
904 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
913 | CPU 1 | : | B=2 | }
933 { B = 7; X = 9; Y = 8; C = &Y }
935 STORE B = 2
937 STORE C = &B LOAD X
938 STORE D = 4 LOAD C (gets &B)
939 LOAD *C (reads B)
946 | |------>| B=2 |----- --->| Y->8 | | of perception on
952 | | : | C=&B |--- | : : +-------+
954 | |------>| D=4 | ----------->| C->&B |------>| |
960 Apparently incorrect ---> | | B->7 |------>| |
961 perception of B (!) | +-------+ | |
966 of coherence of B ----->| B->2 | +-------+
971 In the above example, CPU 2 perceives that B is 7, despite the load of *C
972 (which would be B) coming after the LOAD of C.
975 and the load of *C (ie: B) on CPU 2:
979 { B = 7; X = 9; Y = 8; C = &Y }
981 STORE B = 2
983 STORE C = &B LOAD X
984 STORE D = 4 LOAD C (gets &B)
986 LOAD *C (reads B)
992 | |------>| B=2 |----- --->| Y->8 |
998 | | : | C=&B |--- | : : +-------+
1000 | |------>| D=4 | ----------->| C->&B |------>| |
1010 are perceptible to ----->| B->2 |------>| |
1020 { A = 0, B = 9 }
1023 STORE B=2
1024 LOAD B
1034 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1036 | |------>| B=2 |--- | : :
1039 ---------->| B->2 |------>| |
1051 If, however, a read barrier were to be placed between the load of B and the
1056 { A = 0, B = 9 }
1059 STORE B=2
1060 LOAD B
1071 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1073 | |------>| B=2 |--- | : :
1076 ---------->| B->2 |------>| |
1082 prior to the storage of B ---->| A->1 |------>| |
1092 { A = 0, B = 9 }
1095 STORE B=2
1096 LOAD B
1101 Even though the two loads of A both occur after the load of B, they may both
1108 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1110 | |------>| B=2 |--- | : :
1113 ---------->| B->2 |------>| |
1122 prior to the storage of B ---->| A->1 |------>| 2nd |
1134 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1136 | |------>| B=2 |--- | : :
1139 ---------->| B->2 |------>| |
1154 load of B came up with B == 2. No such guarantee exists for the first load of
1176 LOAD B
1185 --->| B->2 |------>| |
1204 LOAD B
1216 --->| B->2 |------>| |
1238 --->| B->2 |------>| |
1277 CPU A follows a load from the same variable executing on CPU B, then
1278 CPU A's load must either return the same value that CPU B's load did,
1846 *B = b;
1850 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1866 *B = b;
1870 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1910 *B = b;
1920 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1926 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1927 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1928 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1929 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2110 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2119 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2123 *B, *C or *D preceding ACQUIRE M
2124 *A, *B or *C following RELEASE M
2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2671 +--------+ : +--->| Cache B |<------->| |
2689 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2715 <B:modify p=&v> p is now in cache B exclusively
2741 <B:modify p=&v> <D:commit p=&v>
2766 <B:modify p=&v> <D:commit p=&v>
2830 WRITE_ONCE(*B, b);
2839 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2871 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B