Lines Matching refs:after

346      operations specified after the barrier with respect to the other
354      occur in the sequence _before_ all the stores after the write barrier.
379      touched by the load will be perceptible to any loads issued after the data
400      all the LOAD operations specified after the barrier with respect to the
417      the LOAD and STORE operations specified after the barrier with respect to
431      operations after the ACQUIRE operation will appear to happen after the
437      happen after it completes.
451      Memory operations that occur after a RELEASE operation may appear to
457      pair is -not- guaranteed to act as a full memory barrier.  However, after
672 assembly code even after all compiler optimizations have been applied.
784 assertion can fail after the combined three-CPU example completes.  If you
787 that is, just before or just after the "if" statements.  Furthermore,
875 match the loads after the read barrier or the data dependency barrier, and vice
972 (which would be B) coming after the LOAD of C.
1101 Even though the two loads of A both occur after the load of B, they may both
1274 Because CPU 2's load from X in some sense came after CPU 1's store, it
1443      do with the value after the READ_ONCE().  For example, suppose you
1650 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1676      barrier after it, depending on the function.  It isn't guaranteed to
1800      Memory operations issued after the ACQUIRE will be completed after the
1803      Memory operations issued before the ACQUIRE may be completed after
1814      Memory operations issued after the RELEASE may be completed before the
1839 because it is possible for an access preceding the ACQUIRE to happen after the
1962 after it has altered the task state:
1977 which therefore also imply a general memory barrier after setting the state.
2049 values after the sleeper has called set_current_state().  For instance, if the
2065 the sleeper as coming after the change to my_data.  In such a circumstance, the
2294 function has to needlessly get the spinlock again after being woken up.
2306 barrier will appear to happen before all the memory accesses after the barrier
2466 The store to the data register might happen after the second store to the
2772 			<C:read *q>	Reads from v after v updated in cache
2796 cache lines being written back to RAM from a CPU's cache after the device has