Lines Matching refs:D

153 	P = &B		D = *Q;
155 There is an obvious data dependency here, as the value loaded into D depends on
159 	(Q == &A) and (D == 1)
160 	(Q == &B) and (D == 2)
161 	(Q == &B) and (D == 4)
163 Note that CPU 2 will never try and load C into D because the CPU will load P
174 port register (D).  To read internal register 5, the following code might then
178 	x = *D;
182 	STORE *A = 5, x = LOAD *D
183 	x = LOAD *D, STORE *A = 5
197 	WRITE_ONCE(Q, P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
201 	Q = LOAD P, D = LOAD *Q
240 	X = *A; Y = *B; *D = Z;
244 	X = LOAD *A,  Y = LOAD *B,  STORE *D = Z
245 	X = LOAD *A,  STORE *D = Z, Y = LOAD *B
246 	Y = LOAD *B,  X = LOAD *A,  STORE *D = Z
247 	Y = LOAD *B,  STORE *D = Z, X = LOAD *A
248 	STORE *D = Z, X = LOAD *A,  Y = LOAD *B
249 	STORE *D = Z, Y = LOAD *B,  X = LOAD *A
525 			      D = *Q;
530 	(Q == &A) implies (D == 1)
531 	(Q == &B) implies (D == 4)
536 	(Q == &B) and (D == 2) ????
553 			      D = *Q;
580 			      D = M[Q];
899 	STORE D = 4
904 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
919 	|       |------>| D=4  |     }
938 	STORE D = 4		LOAD C (gets &B)
954 	|       |------>| D=4  |    ----------->| C->&B |------>|       |
984 	STORE D = 4		LOAD C (gets &B)
1000 	|       |------>| D=4  |    ----------->| C->&B |------>|       |
1913 	*D = d;
1920 	ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1926 	{*F,*A}, *B,	ACQUIRE, *C, *D,	RELEASE, *E
1927 	*A, *B, *C,	ACQUIRE, *D,		RELEASE, *E, *F
1928 	*A, *B,		ACQUIRE, *C,		RELEASE, *D, *E, *F
1929 	*B,		ACQUIRE, *C, *D,	RELEASE, {*F,*A}, *E
2113 	WRITE_ONCE(*D, d);		WRITE_ONCE(*H, h);
2119 	*E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2123 	*B, *C or *D preceding ACQUIRE M
2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2679 	+--------+  : +--->| Cache D |<------->|        |
2689  (*) an even-numbered cache line may be in cache B, cache D or it may still be
2740 			<D:request p>
2741 	<B:modify p=&v>	<D:commit p=&v>
2742 			<D:read p>
2765 			<D:request p>
2766 	<B:modify p=&v>	<D:commit p=&v>
2767 			<D:read p>
2832 	d = READ_ONCE(*D);
2839 	LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2871 	LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2873 	(Where "LOAD {*C,*D}" is a combined load)
2990 	Appendix D: Formal Specification of the Memory Models
3005 	Appendix D: Formal Specifications of the Memory Models