Lines Matching refs:be

6 instruction. Unfortunately, this alone can't be used to implement the following operations:
17 interrupts, but on the FR-V CPUs, modifying the PSR takes a lot of clock cycles, and it has to be
34  (*) All atomic operations can then be broken down into the following algorithm:
38      (2) Load the value currently in the memory to be modified into a register.
47 	     task pointer in the kernel, and so is guaranteed to be non-zero).
85 load. The VLIW packing ensures they are done simultaneously. The ".p" on the load must not be
91 Then the proposed modification is generated. Note that the old value can be retained if required
105 Such that the branch can then be taken if the operation was aborted.
121 The atomic ops implementation can be made inline or out-of-line by changing the
125  - The resulting kernel image may be smaller
126  - Debugging is easier as atomic ops can just be stepped over and they can be breakpointed
130  - The resulting kernel may be Faster
131    - no out-of-line function calls need to be made