Lines Matching refs:FPGA

1 FPGA Manager Core
8 The FPGA manager core exports a set of functions for programming an FPGA with
11 The FPGA image data itself is very manufacturer specific, but for our purposes
12 it's just binary data.  The FPGA manager core won't parse it.
18 To program the FPGA from a file or from a buffer:
24 Load the FPGA from an image which exists as a buffer in memory.
29 Load the FPGA from an image which exists as a file.  The image file must be on
33 FPGA_MGR_PARTIAL_RECONFIG for partial reconfiguration.  If successful, the FPGA
37 To get/put a reference to a FPGA manager:
44 Given a DT node, get an exclusive reference to a FPGA manager or release
48 To register or unregister the low level FPGA-specific driver:
57 Use of these two functions is described below in "How To Support a new FPGA
61 How to write an image buffer to a supported FPGA
66 /* device node that specifies the FPGA manager to use */
69 /* FPGA image is in this buffer.  count is size of the buffer. */
78 /* Get exclusive control of FPGA manager */
81 /* Load the buffer to the FPGA */
84 /* Release the FPGA manager */
88 How to write an image file to a supported FPGA
93 /* device node that specifies the FPGA manager to use */
96 /* FPGA image is in this file which is in the firmware search path */
104 /* Get exclusive control of FPGA manager */
107 /* Get the firmware image (path) and load it to the FPGA */
110 /* Release the FPGA manager */
114 How to support a new FPGA device
116 To add another FPGA manager, write a driver that implements a set of ops.  The
139 	return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
152 do the programming sequence for this particular FPGA.  These ops return 0 for
160 The .write_init function will prepare the FPGA to receive the image data.
162 The .write function writes a buffer to the FPGA. The buffer may be contain the
163 whole FPGA image or may be a smaller chunk of an FPGA image.  In the latter
167 to put the FPGA into operating mode.
169 The ops include a .state function which will read the hardware FPGA manager and