Lines Matching refs:transfer

20 will want to start a transfer, it will assert a DMA request (DRQ) by
24 parameter: the transfer size. At each clock cycle, it would transfer a
25 byte of data from one buffer to another, until the transfer size has
30 cycle. For example, we may want to transfer as much data as the
35 parameter called the transfer width.
43 transfer into smaller sub-transfers.
58 transfer, and whenever the transfer is started, the controller will go
72 transfer width and the transfer size.
117     - should contain a bitmask of the supported source transfer width
120     - should contain a bitmask of the supported destination transfer
128     - Granularity of the transfer residue reported to dma_set_residue.
179     - The device is able to trigger a dummy transfer that will
188       scatter-gather transfer, with a single chunk to transfer, it's a
207     - If you want to transfer a single contiguous memory buffer,
212     - A cyclic transfer is a transfer where the chunk collection will
218     - The device supports interleaved transfer.
219     - These transfers can transfer data from a non-contiguous buffer
221       transfer data from a non-contiguous data set to a continuous
224       want to transfer a portion of uncompressed data directly to the
231 after each transfer. In case of a ring buffer, they may loop
260        for the transfer being prepared, and should create a hardware
267        during the transfer setup at probe time to avoid putting to
272        particular transfer.
288        and starts the transfer. Whenever that transfer is done, it
298      - In the case of a cyclic transfer, it should only take into
319      - Pauses a transfer on the channel
324      - Resumes a transfer on the channel
337     - Should be called at the end of an async TX transfer, and can be
363       it can resubmit the transfer right after its completion.
376 that handles the end of transfer interrupts in the handler, but defer
377 most work to a tasklet, including the start of a new transfer whenever
378 the previous transfer ended.
380 This is a rather inefficient design though, because the inter-transfer
383 in between, which will slow down the global transfer rate.
386 transfer in your tasklet, move that part to the interrupt handler in