Lines Matching refs:and

8      secondary fifo, s/w reset control and internal mux for root clk src.
12      and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
16      with only external dma and more no.of root clk sampling frequencies.
21 - reg: physical base address of the controller and length of memory mapped
23 - dmas: list of DMA controller phandle and DMA request line ordered pairs.
26 - clocks: Handle to iis clock and RCLK source clk.
28   i2s0 uses some base clks from CMU and some are from audio subsystem internal
29   clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
31   i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
32   be "iis" and "i2s_opclk0".
33   "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
34   clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
51 The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available
54 and then not use the I2S node as a clock supplier.