Lines Matching refs:the
6 to change. Some of the compatible strings that contain only generic names
8 the integration of the block with the rest of the chip.
15 This node defines the base address and range for the
16 defined DCSR Memory Map. Child nodes will describe the individual
25 The DCSR space exists in the memory-mapped bus.
30 Definition: A standard property. Defines the number of cells
36 Definition: A standard property. Defines the number of cells
37 or representing the size of physical addresses in
43 Definition: A standard property. Specifies the physical address
44 range of the DCSR space.
57 This node represents the region of DCSR space allocated to the EPU
69 Definition: Specifies the interrupts generated by the EPU.
70 The value of the interrupts property consists of three
71 interrupt specifiers. The format of the specifier is defined
72 by the binding document describing the node's interrupt parent.
74 The EPU counters can be configured to assert the performance
76 match. Which counter asserted the interrupt is captured in an EPU
80 two interrupt signals based on debug event sources within the SoC.
82 Which event source asserted the interrupt is captured in an EPU
91 to the interrupt parent to which the child domain
97 Definition: A standard property. Specifies the physical address
98 offset and length of the DCSR space registers of the device
114 This node represents the region of DCSR space allocated to the NPC
126 Definition: A standard property. Specifies the physical address
127 offset and length of the DCSR space registers of the device
129 The Nexus Port controller occupies two regions in the DCSR space
132 The first register range describes the Nexus Port Controller
135 The second register range describes the Nexus Port Controller
137 which stages the nexus trace data for transmission via the Aurora port
138 or to a DDR based trace buffer. In some configurations the NPC trace
139 buffer can be the only trace buffer used.
151 This node represents the region of DCSR space allocated to the NXC
163 Definition: A standard property. Specifies the physical address
164 offset and length of the DCSR space registers of the device
175 This node represents the region of DCSR space allocated to
176 the CoreNet Debug controller.
188 Definition: A standard property. Specifies the physical address
189 offset and length of the DCSR space registers of the device
191 The CoreNet Debug controller occupies two regions in the DCSR space
194 The first register range describes the CoreNet Debug Controller
197 The second register range describes the CoreNet Debug Controller
209 This node represents the region of DCSR space allocated to
210 the DPAA Debug Controller. This controller controls debug configuration
211 for the QMAN and FMAN blocks.
218 Definition: Must include both an identifier specific to the SoC
219 or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
225 Definition: A standard property. Specifies the physical address
226 offset and length of the DCSR space registers of the device
238 This node represents the region of DCSR space allocated to
239 the OCN Debug Controller.
246 Definition: Must include both an identifier specific to the SoC
247 or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
253 Definition: A standard property. Specifies the physical address
254 offset and length of the DCSR space registers of the device
266 This node represents the region of DCSR space allocated to
267 the OCN Debug Controller.
284 Definition: A standard property. Specifies the physical address
285 offset and length of the DCSR space registers of the device
298 This node represents the region of DCSR space allocated to
299 the NAL Controller.
306 Definition: Must include both an identifier specific to the SoC
307 or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
313 Definition: A standard property. Specifies the physical address
314 offset and length of the DCSR space registers of the device
327 This node represents the region of DCSR space allocated to
328 the RCPM Debug Controller. This functionlity is limited to the
329 control the debug operations of the SoC and cores.
336 Definition: Must include both an identifier specific to the SoC
337 or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
343 Definition: A standard property. Specifies the physical address
344 offset and length of the DCSR space registers of the device
356 This node represents the region of DCSR space allocated to
357 the Core Service Bridge Proxies.
358 There is one Core Service Bridge Proxy device for each CPU in the system.
359 This functionlity provides access to the debug operations of the CPU.
366 Definition: Must include both an identifier specific to the cpu
367 of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
377 Definition: A standard property. Specifies the physical address
378 offset and length of the DCSR space registers of the device