Lines Matching refs:DCSR

2 Debug Control and Status Register (DCSR) Binding
16 defined DCSR Memory Map. Child nodes will describe the individual
25 	The DCSR space exists in the memory-mapped bus.
44 	range of the DCSR space.
57 This node represents the region of DCSR space allocated to the EPU
98 	offset and length of the DCSR space registers of the device
114 This node represents the region of DCSR space allocated to the NPC
127 	offset and length of the DCSR space registers of the device
129 	The Nexus Port controller occupies two regions in the DCSR space
151 This node represents the region of DCSR space allocated to the NXC
164 	offset and length of the DCSR space registers of the device
175 This node represents the region of DCSR space allocated to
189 	offset and length of the DCSR space registers of the device
191 	The CoreNet Debug controller occupies two regions in the DCSR space
209 This node represents the region of DCSR space allocated to
226 	offset and length of the DCSR space registers of the device
238 This node represents the region of DCSR space allocated to
254 	offset and length of the DCSR space registers of the device
266 This node represents the region of DCSR space allocated to
285 	offset and length of the DCSR space registers of the device
298 This node represents the region of DCSR space allocated to
314 	offset and length of the DCSR space registers of the device
327 This node represents the region of DCSR space allocated to
344 	offset and length of the DCSR space registers of the device
356 This node represents the region of DCSR space allocated to
378 	offset and length of the DCSR space registers of the device