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3 This document describes the device tree binding of the pin mapping hardware
4 modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
5 Digicolor series of SoCs.
12 - reg: Base address of the General Purpose Pin Mapping register block and the
13   size of the block.
32 For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
36 Each pin configuration node is a sub-node of the pin controller node and is a
37 container of an arbitrary number of subnodes, called pin group nodes in this
40 Please refer to the pinctrl-bindings.txt in this directory for details of the
41 common pinctrl bindings used by client devices, including the definition of a
46 A pin group node specifies the desired pin mux for an arbitrary number of
47 pins. The name of the pin group node is optional and not used.
52 The pin group node accepts a subset of the generic pin config properties. For
58 - pins: Multiple strings. Specifies the name(s) of one or more pins to be
59   configured by this node. The format of a pin name string is "GP_xy", where x
61 - function: String. Specifies the pin mux selection. Values must be one of:
85 "client select" for the Rx and Tx signals of uart0. The uart0 node references