Lines Matching refs:mmc

33 - cap-mmc-highspeed: MMC high-speed timing is supported
40 - cap-mmc-hw-reset: eMMC hardware reset is supported
43 - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
44 - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
45 - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
46 - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
47 - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
48 - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
83 - mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
123 	mmc-pwrseq = <&sdhci0_pwrseq>
128 mmc3: mmc@01c12000 {
137 	mmc-pwrseq = <&sdhci0_pwrseq>