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4 Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
9 those busses to the MSI controllers which they are capable of using,
12 MSIs are distinguished by some combination of:
17   they can address. An MSI controller may feature a number of doorbells.
27   taken through the memory system (i.e. it is a property of the combination of
28   MSI controller and device rather than a property of either in isolation).
35 address by some master. An MSI controller may feature a number of doorbells.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
50   The meaning of the msi-specifier is defined by the device tree binding of
64 - msi-parent: A list of phandle + msi-specifier pairs, one for each MSI
65   controller which the device is capable of using.
67   This property is unordered, and MSIs may be allocated from any combination of
70   If a device has restrictions on the allocation of MSIs, these restrictions
75   and the set of MSIs they can potentially generate.
131 		 * Can generate MSIs to all of the MSI controllers.