Lines Matching refs:of

23 SEC 4 h/w can process requests from 2 types of sources.
30 such as the P4080.  The number of simultaneous dequeues the QI can make is
31 equal to the number of Descriptor Controller (DECO) engines in a particular
46     Node defines the base address of the SEC 4 block.
47     This block specifies the address range of all global
62       Definition: A standard property. Define the 'ERA' of the SEC
68        Definition: A standard property.  Defines the number of cells
74        Definition: A standard property.  Defines the number of cells
75            for representing the size of physical addresses in
82           address and length of the SEC4 configuration registers.
89            range of the SEC 4.0 register space (-SNVS not included).  A
97            device.  The value of the interrupts property
98            consists of one interrupt specifier. The format
99            of the specifier is defined by the binding document
110       Usage: required if SEC 4.0 requires explicit enablement of clocks
112       Definition:  A list of phandle and clock specifier pairs describing
116       Usage: required if SEC 4.0 requires explicit enablement of clocks
118       Definition: A list of clock name strings in the same order as the
145     Child of the crypto node defines data processing interface to SEC 4
146     across the peripheral bus for purposes of processing
150     the address range of this node.
177            device.  The value of the interrupts property
178            consists of one interrupt specifier. The format
179            of the specifier is defined by the binding document
202   Child node of the crypto node.  Defines a register space that
203   contains up to 5 sets of addresses and their lengths (sizes) that
218        Definition: A standard property.  Defines the number of cells
220            have a value of 1.
225        Definition: A standard property.  Defines the number of cells
226            for representing the size of physical addresses in
227            child nodes.  Must have a value of 1.
240            range of the SEC 4 register space (-SNVS not included).  A
256   perform run-time integrity check of memory areas that should not modified.
272           1. The location of the RTIC memory address & length registers.
280            followed by the length of the HW partition to be checked;
320           address and length of the SEC4 configuration
326        Definition: A standard property.  Defines the number of cells
328            have a value of 1.
333        Definition: A standard property.  Defines the number of cells
334            for representing the size of physical addresses in
335            child nodes.  Must have a value of 1.
341            range of the SNVS register space.  A triplet that includes
348            device.  The value of the interrupts property
349            consists of one interrupt specifier. The format
350            of the specifier is defined by the binding document
383 	   device.  The value of the interrupts property
384 	   consists of one interrupt specifier. The format
385 	   of the specifier is defined by the binding document
410   by SNVS ONOFF, the driver can report the status of POWER key and wakeup