Lines Matching refs:SEC

2 SEC 4 Device Tree Binding
7    -SEC 4 Node
15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
23 SEC 4 h/w can process requests from 2 types of sources.
24 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
25 2. Job Rings (HW interface between cores & SEC 4 registers).
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
32 SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
42 SEC 4 Node
46     Node defines the base address of the SEC 4 block.
48     configuration registers for the SEC 4 block.  It
50     (RTIC) function within the SEC 4 block.
62       Definition: A standard property. Define the 'ERA' of the SEC
89            range of the SEC 4.0 register space (-SNVS not included).  A
110       Usage: required if SEC 4.0 requires explicit enablement of clocks
113           the clocks required for enabling and disabling SEC 4.0.
116       Usage: required if SEC 4.0 requires explicit enablement of clocks
145     Child of the crypto node defines data processing interface to SEC 4
240            range of the SEC 4 register space (-SNVS not included).  A