Lines Matching refs:clock

3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 	"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 	"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 	"apm,xgene-device-clock" - for a X-Gene device clock
14 - reg : shall be the physical PLL register address for the pll clock.
15 - clocks : shall be the input parent clock phandle for the clock. This should
16 	be the reference clock.
17 - #clock-cells : shall be set to 1.
18 - clock-output-names : shall be the name of the PLL referenced by derive
19   clock.
21 - clock-names : shall be the name of the PLL. If missing, use the device name.
31 - clocks : shall be the input parent clock phandle for the clock.
32 - #clock-cells : shall be set to 1.
33 - clock-output-names : shall be the name of the device referenced.
35 - clock-names : shall be the name of the device clock. If missing, use the
51 		compatible = "apm,xgene-pcppll-clock";
52 		#clock-cells = <1>;
54 		clock-names = "pcppll";
56 		clock-output-names = "pcppll";
61 		compatible = "apm,xgene-socpll-clock";
62 		#clock-cells = <1>;
64 		clock-names = "socpll";
66 		clock-output-names = "socpll";
71 		compatible = "apm,xgene-device-clock";
72 		#clock-cells = <1>;
74 		clock-names = "qmlclk";
77 		clock-output-names = "qmlclk";
81 		compatible = "apm,xgene-device-clock";
82 		#clock-cells = <1>;
84 		clock-names = "ethclk";
90 		clock-output-names = "ethclk";
94 		compatible = "apm,xgene-device-clock";
95 		#clock-cells = <1>;
97 		clock-names = "apbclk";
109 		clock-output-names = "apbclk";