Lines Matching refs:be

8 - compatible : shall be one of the following:
14 - reg : shall be the physical PLL register address for the pll clock.
15 - clocks : shall be the input parent clock phandle for the clock. This should
16 	be the reference clock.
17 - #clock-cells : shall be set to 1.
18 - clock-output-names : shall be the name of the PLL referenced by derive
21 - clock-names : shall be the name of the PLL. If missing, use the device name.
24 - reg : shall be a list of address and length pairs describing the CSR
25          reset and/or the divider. Either may be omitted, but at least
26          one must be present.
27  - reg-names : shall be a string list describing the reg resource. This
31 - clocks : shall be the input parent clock phandle for the clock.
32 - #clock-cells : shall be set to 1.
33 - clock-output-names : shall be the name of the device referenced.
35 - clock-names : shall be the name of the device clock. If missing, use the