Lines Matching refs:clock
1 Binding for Texas Instruments DPLL clock.
5 This binding uses the common clock binding[1]. It assumes a
7 (reference clock and bypass clock), with digital phase locked
8 loop logic for multiplying the input clock to a desired output
9 clock. This clock also typically supports different operation
12 for the actual DPLL clock.
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
28 "ti,am3-dpll-no-gate-clock",
29 "ti,am3-dpll-j-type-clock",
30 "ti,am3-dpll-no-gate-j-type-clock",
31 "ti,am3-dpll-clock",
32 "ti,am3-dpll-core-clock",
33 "ti,am3-dpll-x2-clock",
34 "ti,omap2-dpll-core-clock",
36 - #clock-cells : from common clock binding; shall be set to 0.
37 - clocks : link phandles of parent clocks, first entry lists reference clock
38 and second entry bypass clock
52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
57 #clock-cells = <0>;
58 compatible = "ti,omap4-dpll-core-clock";
64 #clock-cells = <0>;
65 compatible = "ti,omap3-dpll-clock";
74 #clock-cells = <0>;
75 compatible = "ti,am3-dpll-core-clock";
81 #clock-cells = <0>;
82 compatible = "ti,omap2-dpll-core-clock";