Lines Matching refs:source

26 - silabs,pll-source: pair of (number, source) for each pll. Allows
27   to overwrite clock source of pll A (number=0) or B (number=1).
39 - silabs,clock-source: source clock of the output divider stage N, shall be
45 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
77 		/* connect xtal input as source of pll0 and pll1 */
78 		silabs,pll-source = <0 0>, <1 0>;
83 		 * - pll0 as clock source of multisynth0
84 		 * - multisynth0 as clock source of output divider
91 			silabs,multisynth-source = <0>;
92 			silabs,clock-source = <0>;
100 		 * - pll1 as clock source of multisynth1
101 		 * - multisynth1 as clock source of output divider
107 			silabs,multisynth-source = <1>;
108 			silabs,clock-source = <0>;
114 		 * - xtal as clock source of output divider
118 			silabs,clock-source = <2>;