Lines Matching refs:clock

4 Generator (CPG). Their clock input is divided by a configurable factor from 1
10     - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11     - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
12     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
13     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
14     - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
15     - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
16     - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
17     and "renesas,cpg-div6-clock" as a fallback.
18   - reg: Base address and length of the memory resource used by the DIV6 clock
19   - clocks: Reference to the parent clock(s); either one, four, or eight
22   - #clock-cells: Must be 0
23   - clock-output-names: The name of the clock as a free-form string
30 		compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
34 		#clock-cells = <0>;
35 		clock-output-names = "sdhi2ck";