Lines Matching refs:clock

3 The Samsung Audio Subsystem clock controller generates and supplies clocks
4 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
10   - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11   - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
13   - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
17 - #clock-cells: should be 1.
20   - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
24   - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
26   - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
28   - sclk_pcm_in: PCM clock, parent of sclk_pcm.  "sclk_pcm0" is used if not
31 - clock-names: Aliases for the above clocks. They should be "pll_ref",
34 The following is the list of clocks generated by the controller. Each clock is
36 clock which they consume. Some of the clocks are available only on a particular
56 Example 1: An example of a clock controller node using the default input
57 	   clock names is listed below.
59 clock_audss: audss-clock-controller@3810000 {
60 	compatible = "samsung,exynos5250-audss-clock";
62 	#clock-cells = <1>;
65 Example 2: An example of a clock controller node with the input clocks
68 clock_audss: audss-clock-controller@3810000 {
69 	compatible = "samsung,exynos5250-audss-clock";
71 	#clock-cells = <1>;
72 	clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
74 	clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
77 Example 3: I2S controller node that consumes the clock generated by the clock
78            controller. Refer to the standard clock bindings for information
79            about 'clocks' and 'clock-names' property.
93 	clock-names = "iis", "i2s_opclk0", "i2s_opclk1",