Lines Matching refs:clock

3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 	"altr,socfpga-pll-clock" - for a PLL clock
10 	"altr,socfpga-perip-clock" - The peripheral clock divided from the
11 		PLL clock.
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
24 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
27 	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
29 	hold/delay times that is needed for the SD/MMC CIU clock. The values of both