Lines Matching refs:to
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
13 Standby: Standby does a little more in addition to architectural clock gating.
15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
16 trigger to execute the SPM state machine. The SPM state machine waits for the
17 interrupt to trigger the core back in to active. This triggers the cache
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
19 the SPM state machine out of its wait, the next step is to ensure that the
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
23 configured to execute this state by default and after executing every other
28 voltage may be reduced to the minimum value needed to keep the processor
29 registers active. The SPM should be configured to execute the retention
30 sequence and would wait for interrupt, before restoring the cpu to execution
35 to indicate a core entering a power down state without consulting any other
37 sequence for this idle state is programmed to power down the supply to the
38 core, wait for the interrupt, restore power to the core, and ensure the
39 system state including cache hierarchy is ready before allowing core to
40 resume. Applying power and resetting the core causes the core to warmboot
41 back into Elevation Level (EL) which trampolines the control back to the
42 kernel. Entering a power down state for the cpu, needs to be done by trapping
43 into a EL. Failing to do so, would result in a crash enforced by the warm boot
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
47 Power Collapse: This state is similar to the SPC mode, but distinguishes
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
55 with the Resource power manager (RPM) processor in the SoC to indicate a