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4 implementations of the L2 cache controller with compatible programming models.
5 Some of the properties that are just prefixed "cache-*" are taken from section
6 3.7.3 of the ePAPR v1.1 specification which can be found at:
13 - compatible : should be one of:
31 - reg : Physical base address and size of cache controller's memory mapped
36 - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
38   without setup latency control should use a value of 0.
39 - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
43 - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
44 - arm,filter-ranges : <start length> Starting address and length of window to
51 - cache-size : specifies the size in bytes of the cache
52 - cache-sets : specifies the number of associativity sets of the cache
53 - cache-block-size : specifies the size in bytes of a cache block
54 - cache-line-size : specifies the size in bytes of a line in the cache,
70 - arm,shared-override : The default behavior of the pl310 cache controller with