Lines Matching refs:arm

14   "arm,pl310-cache"
15   "arm,l220-cache"
16   "arm,l210-cache"
28      with arm,pl310-cache controller.
36 - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
39 - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
43 - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
44 - arm,filter-ranges : <start length> Starting address and length of window to
47 - arm,io-coherent : indicates that the system is operating in an hardware
48   I/O coherent mode. Valid only when the arm,pl310-cache compatible
60 - arm,double-linefill : Override double linefill enable setting. Enable if
62 - arm,double-linefill-incr : Override double linefill on INCR read. Enable
64 - arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
66 - arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
68 - arm,prefetch-offset : Override prefetch offset value. Valid values are
70 - arm,shared-override : The default behavior of the pl310 cache controller with
85         compatible = "arm,pl310-cache";
87         arm,data-latency = <1 1 1>;
88         arm,tag-latency = <2 2 2>;
89         arm,filter-ranges = <0x80000000 0x8000000>;