Lines Matching refs:CPU
11 wfi to power gating) according to OS PM policies. The CPU states representing
17 power states an ARM CPU can be put into are identified by the following list:
25 The power states described in the SBSA document define the basic CPU states on
46 The following diagram depicts the CPU execution phases and related timing
59 Diagram 1: CPU idle state execution phases
61 EXEC: Normal CPU execution.
66 (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
76 EXIT: Period during which the CPU is brought back to operational
86 CPU being able to execute normal code again. If not specified, this is assumed
91 An idle CPU requires the expected min-residency time to select the most
93 (ie wake-up) that causes the CPU to return to the EXEC phase.
96 for CPUs in the system by detecting how long will it take to get a CPU out
102 (eg waking-up) the CPU with the shortest wake-up latency.
106 the worst case since it depends on the CPU operating conditions, ie caches
111 worst case wake-up latency it can incur if a CPU is allowed to enter an
216 states nodes. If the system does not provide CPU
222 subnodes describe the CPU idle states.
278 Definition: if present the CPU local timer control logic is
308 signaling of a wake-up event and the CPU being