Lines Matching refs:be

18 hypervisor code, or it may just be a handful of instructions for
48 The device tree blob (dtb) must be placed on an 8-byte boundary and must
49 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
50 using blocks of up to 2 megabytes in size, it must not be placed within
51 any 2M region which must be mapped with any specific attributes.
53 NOTE: versions prior to v4.2 also require that the DTB be placed within
62 therefore requires decompression (gzip etc.) to be performed by the boot
101   little-endian and must be respected.  Where image_size is zero,
102   text_offset can be assumed to be 0x80000.
119 The Image must be placed text_offset bytes from a 2MB aligned base
124 image has no special significance to the kernel, and may be used for
126 At least image_size bytes from the start of the image must be free for
131 memreserve region in the device tree) will be considered as available to
134 Before jumping into the kernel, the following conditions must be met:
147   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
149   The CPU must be in either EL2 (RECOMMENDED in order to have access to
153   The MMU must be off.
154   Instruction cache may be on or off.
155   The address range corresponding to the loaded kernel image must be
160   operations must be configured and may be enabled.
162   operations (not recommended) must be configured and disabled.
165   CNTFRQ must be programmed with the timer frequency and CNTVOFF must
166   be programmed with a consistent value on all CPUs.  If entering the
171   All CPUs to be booted by the kernel must be part of the same coherency
178   the kernel image will be entered must be initialised by software at a
181   For systems with a GICv3 interrupt controller to be used in v3 mode:
183     ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
184     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
186     ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
187     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
190   For systems with a GICv3 interrupt controller to be used in
193     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
195     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
219   device tree) polling their cpu-release-addr location, which must be
220   contained in the reserved region.  A wfe instruction may be inserted
221   to reduce the overhead of the busy-loop and a sev will be issued by
224   value.  The value will be written as a single 64-bit little-endian