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11 and a DTCM (data TCM). The DTCM can not contain any
14 minimum configuration is 4KiB ITCM and 4KiB DTCM.
17 location and size of TCM memories. arch/arm/include/asm/cputype.h
22 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
26 Registers" at the ARM site) that can report and modify the location
27 size of TCM memories at runtime. This is used to read out and modify
28 TCM location and size. Notice that this is not a MMU table: you
39 will map ITCM to 0xfffe0000 and on, and DTCM to 0xfffe8000 and
40 on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
45 be able to lock and hide one of the banks for use by the secure
50 - FIQ and other interrupt handlers that need deterministic
51   timing and cannot wait for cache misses.
55   the CPU and then we hang inside ITCM waiting for an
64 - Define the physical address and size of ITCM and DTCM.
68 - Tag data and constants to be allocated to DTCM and ITCM.
71   allocation pool with gen_pool_create() and gen_pool_add()
72   and provice tcm_alloc() and tcm_free() for this
83 Since these are marked to become long_calls and you may want