Lines Matching refs:pin

5 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
13 mechanism is introduced from PXA3xx to completely move the pin-mux functions
14 out of the GPIO controller. In addition to pin-mux configurations, the MFP
16 detection of each pin.  Below is a diagram of internal connections between
42 mean it's dedicated for GPIO19, only as a hint that internally this pin
61   3. Low power state for each pin is now controlled by MFP, this means the
69 mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
86    because pin configuration definitions may conflict in these file (i.e.
93    NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
97 2. prepare an array for the initial pin configurations, e.g.:
121    a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
125    b) when there is only one possible pin configurations for a component,
129    c) if by board design, a pin can be configured to wake up the system
137    to indicate that this pin has the capability of wake-up the system,
139    pin _will_ wakeup the system, it will only when set_irq_wake() is
143    d) although PXA3xx MFP supports edge detection on each pin, the
164   Bit 4:   EDGE_RISE_EN - enable detection of rising edge on this pin
165   Bit 5:   EDGE_FALL_EN - enable detection of falling edge on this pin
166   Bit 6:   EDGE_CLEAR   - disable edge detection on this pin
168   Bit 8:   SLEEP_DATA   - output data on the pin during low power modes
170   Bit 13:  PULLDOWN_EN  - enable the internal pull-down resistor on this pin
171   Bit 14:  PULLUP_EN    - enable the internal pull-up resistor on this pin
189 Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
192 The basic idea of this design is to introduce definitions for all possible pin
203     1. Unified pin definitions - enum constants for all configurable pins
208   for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
213   for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
226   for implementation of the pin configuration to take effect for the actual
255    * 		  pin drive strength
259    * 		  pin drive strength and low power mode
262    Examples of pin configurations are:
270    NOTE: this is the default setting of this pin being configured as SSP3_RXD
278    Register settings on PXA3xx for a pin configuration is actually very
283    The conversion from a generic pin configuration to the actual register