Lines Matching refs:in

32 kernel will use for volatile data storage in the system.  It performs
33 this in a machine dependent manner.  (It may use internal algorithms
35 the RAM in the machine, or any other method the boot loader designer
52 serial format options as described in
68 should be passed to the kernel in register r1.
82 boot data is passed to the kernel in register r2.
93 Any number of tags can be placed in the list.  It is undefined
95 previous tag, or whether it replaces the information in its
110 The tagged list should be stored in system RAM.
112 The tagged list must be placed in a region of memory where neither
114 it.  The recommended placement is in the first 16KiB of RAM.
121 dtb format is documented in Documentation/devicetree/booting-without-of.txt.
128 placed in a region of memory where the kernel decompressor will not
140 If an initramfs is in use then, as with the dtb, it must be placed in
156 is stored in flash, and is linked correctly to be run from flash,
157 then it is legal for the boot loader to call the zImage in flash
160 The zImage may also be placed in system RAM and called there.  The
161 kernel should be placed in the first 128MiB of RAM.  It is recommended
162 that it is loaded above 32MiB in order to avoid the need to relocate
178   r1 = machine type number discovered in (3) above.
179   r2 = physical address of tagged list in system RAM, or
180        physical address of device tree block (dtb) in system RAM
186   CPU must be in SVC mode.  (A special exception exists for Angel)
189   entered in HYP mode in order to enable the kernel to make full use of
191   unless the virtualisations are already in use by a pre-installed
194   If the kernel is not entered in HYP mode for any reason, it must be
195   entered in SVC mode.
202   If the kernel is entered in HYP mode, the above requirements apply to
203   the HYP mode configuration in addition to the ordinary PL1 (privileged
207   possible.  Except for entering in HYP mode, the system configuration
215   made in ARM state, even for a Thumb-2 kernel.
218   Cortex-M class CPUs, the entry must be made in Thumb state.